|کد مقاله||سال انتشار||مقاله انگلیسی||ترجمه فارسی||تعداد کلمات|
|140436||2017||5 صفحه PDF||سفارش دهید||2603 کلمه|
Publisher : Elsevier - Science Direct (الزویر - ساینس دایرکت)
Journal : Microelectronics Reliability, Volumes 76â77, September 2017, Pages 680-684
The electrostatic discharge (ESD) protection is pivotal for advanced CMOS technology manufacturing. Today, several robust solutions are available on the market with sufficient robustness and compliance with the ESD window. In the context of solution optimization and exploration of the initial performance limits it is interesting to investigate a protection beyond its initial feature specification (the usual target is: 1Â kV HBM, 250Â V CDM). This analysis contributes to a better understanding of the internal behaviour and allows us to push the final performance limits of the device. This study is based on a single SCR/diode device where ESD and EMI in the device are extracted to localize the possible weak spots. 3D simulation approach allocates the potential damage locations that are confirmed by failures analysis. The results are useful for improving the device robustness against ESD events and lead to more competitive design. Moreover, it is well known that the fail mechanism involves several physical, electrical and layout parameters with their variabilities. We conclude that additional information of magnetic field intensities and current densities are useful to enhance the understanding of the failure events.