دانلود مقاله ISI انگلیسی شماره 140441
کد مقاله سال انتشار مقاله انگلیسی ترجمه فارسی تعداد کلمات
140441 2017 6 صفحه PDF سفارش دهید 4355 کلمه
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عنوان انگلیسی
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits
منبع

Publisher : Elsevier - Science Direct (الزویر - ساینس دایرکت)

Journal : Solid-State Electronics, Volume 128, February 2017, Pages 37-42

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پیش نمایش مقاله

چکیده انگلیسی

In this work, a benchmark for low-power digital applications of a III-V TFET technology platform against a conventional CMOS FinFET technology node is proposed. The analysis focuses on full-adder circuits, which are commonly identified as representative of the digital logic environment. 28T and 24T topologies, implemented in complementary-logic and transmission-gate logic, respectively, are investigated. Transient simulations are performed with a purpose-built test-bench on each single-bit full adder solution. The extracted delays and energy characteristics are post-processed and translated into figures-of-merit for multi-bit ripple-carry-adders. Trends related to the different full-adder implementations (for the same device technology platform) and to the different technology platforms (for the same full-adder topology) are presented and discussed.

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