دانلود مقاله ISI انگلیسی شماره 140478
کد مقاله سال انتشار مقاله انگلیسی ترجمه فارسی تعداد کلمات
140478 2018 14 صفحه PDF سفارش دهید 8333 کلمه
خرید مقاله
پس از پرداخت، فوراً می توانید مقاله را دانلود فرمایید.
عنوان انگلیسی
Quantification of the likelihood of single event multiple transients in logic circuits in bulk CMOS technology
منبع

Publisher : Elsevier - Science Direct (الزویر - ساینس دایرکت)

Journal : Microelectronics Journal, Volume 72, February 2018, Pages 86-99

پیش نمایش مقاله
پیش نمایش مقاله

چکیده انگلیسی

It is well known that high-energy particle strikes on an integrated circuit can cause circuit errors. We quantify the fraction of a layout which is susceptible to multiple transients, through the notion of critical area fraction (CAF). We perform a 2D-study on a layout of 65 nm planar transistors to evaluate maximum values of CAF. We find that CAF can be as high as 1, that is, 100% of the layout area is vulnerable. Potentials of adjacent source/drain regions play a significant role in increasing the CAF and simple layout techniques do not reduce the CAF substantially. We confirm these observations through 3D simulations of inverter layouts. A key observation is that, CAF is high in the region of the layout which contains small gates. At the circuit-level, multiple transients not only cause multiple errors, they also merge to create wider transient increasing its capture probability. A circuit-aware placement of vulnerable gates and alternate latch designs may be required to alleviate the problem.

خرید مقاله
پس از پرداخت، فوراً می توانید مقاله را دانلود فرمایید.