|کد مقاله||سال انتشار||مقاله انگلیسی||ترجمه فارسی||تعداد کلمات|
|140495||2017||5 صفحه PDF||سفارش دهید||2948 کلمه|
Publisher : Elsevier - Science Direct (الزویر - ساینس دایرکت)
Journal : Microelectronics Journal, Volume 66, August 2017, Pages 84-88
This paper presents a new low-power and area-efficient parallel binary comparator design based on prefix tree structure. Due to its wide usage in central processing units, optimizing binary comparator for low power applications are need of the hour. A novel EX-OR-NOR gate is used in proposed binary comparator as pre-encoder to reduce area, power and delay. The simulation results performed using CADENCE for CMOS 180Â nm â technology. The paper proposes two binary comparator architectures with improved performance. The proposed architecture result in a power reduction upto 25%, area (number of transistors) reduces upto 36% and improves the delay performance 27% compared to existing technique.