|کد مقاله||سال انتشار||مقاله انگلیسی||ترجمه فارسی||تعداد کلمات|
|140527||2018||14 صفحه PDF||سفارش دهید||7328 کلمه|
Publisher : Elsevier - Science Direct (الزویر - ساینس دایرکت)
Journal : Microelectronics Journal, Volume 74, April 2018, Pages 127-140
The sub-threshold circuit design is regarded as a promising technique to provide considerable power reduction for ultra-low-power applications under tight energy constraints. This paper presents Power-Gating Sub-Threshold Source-Coupled Logic (PG-STSCL), which employs the fine-grain power gating at the gate level. It introduces isolation and retention circuits to ensure reliable propagation of data along a pipeline of power gated circuits, called a micro-pipeline. While the conventional STSCL circuits can considerably cut down the active power consumption, they have the drawback of continuous static current flow. To overcome this drawback, the proposed architecture shuts off the static current by utilizing the fine-grain power-gating technique. We have designed a 32-bit adder based on the proposed PG-STSCL gates in a 65â¯nm CMOS technology. The adder was simulated and compared to reference adders using standard CMOS gates, and conventional STSCL gates. Simulations demonstrated that the proposed gates provide a power reduction of 89.56% and 99.78% when compared to the standard CMOS and STSCL gates, respectively.