|کد مقاله||سال انتشار||مقاله انگلیسی||ترجمه فارسی||تعداد کلمات|
|140541||2018||9 صفحه PDF||سفارش دهید||6448 کلمه|
Publisher : Elsevier - Science Direct (الزویر - ساینس دایرکت)
Journal : Microelectronics Reliability, Volume 83, April 2018, Pages 127-135
There are many Radiation Hardened by Design (RHBD) architectures presented in the literature to mitigate Single Event Upset (SEU) in a storage element, a latch. Nevertheless, the design of a SEU hardened latch is being continuously improved with respect to reliability, performance, power consumption and area overhead. SEU mitigating techniques by design focus on reducing criticality of sensitive nodes in a latch. Sensitive node(s) in a latch could be an active and/or a high impedance node(s). In this paper, we have classified previously presented SEU hardened by design latch architectures and reviewed SEU mechanisms in selected RHBD latch architectures on Complementary Metal Oxide Semiconductor (CMOS) technology models. Simulation studies using latest fault simulation model have been carried out. Simulation results have revealed some interesting observations described in this paper. Our findings, based on analyses, will provide valuable design inputs for futuristic RHBD latches with advanced technology nodes.