|کد مقاله||سال انتشار||مقاله انگلیسی||ترجمه فارسی||تعداد کلمات|
|140543||2017||9 صفحه PDF||سفارش دهید||3042 کلمه|
Publisher : Elsevier - Science Direct (الزویر - ساینس دایرکت)
Journal : Solid-State Electronics, Volume 137, November 2017, Pages 128-133
The downsizing of CMOS technology into the decananometer range has called for the redesign of the ESD protection devices because of the constraints of lower operation voltage and smaller breakdown voltage of the ultrathin gate oxide. In this work, we had developed a two-dimensional diode-triggered silicon-controlled rectifier (TD-DTSCR) structure to cope with the narrowed ESD design window in the 28Â nm CMOS technology. A sufficient large SCR trigger voltage was obtained by directing the triggering current to both longitude and lateral directions, through two parasitic diodes and the P-Well, so as to save the chip area for realization. Optimization was done by varying several device parameters and the best ESD robustness obtained was 53.7Â mA/Î¼m which was about 65% larger than that of a simple SCR with the same width of 30Â Î¼m and realized using the same technology. Failure analysis was also conducted to identify the possible weak spots of the proposed structure.