|کد مقاله||سال انتشار||مقاله انگلیسی||ترجمه فارسی||تعداد کلمات|
|140581||2018||6 صفحه PDF||سفارش دهید||3653 کلمه|
Publisher : Elsevier - Science Direct (الزویر - ساینس دایرکت)
Journal : Microelectronics Journal, Volume 75, May 2018, Pages 35-40
As technology continues to shrink, the challenges of developing manufacturing tests for integrated circuits become more difficult to address. To detect parametric faults of new generation of integrated circuits such as 3D ICs, on-chip short-time intervals have to be accurately measured. The accuracy of an on-chip time measurement module is heavily affected by process, supply voltage, and temperature (PVT) variations. This paper presents a new on-chip time measurement scheme where the undesired effects of PVT variations are attenuated significantly. Two Delay Locked Loops (DLLs) are utilized to implement a robust Vernier delay line to measure on-chip time intervals. Measurement results from a fabricated prototype using CMOS 0.18â¯Î¼m technology indicate that the proposed DLL based TDC reduces the effects of PVT by more than tenfold compared to the conventional on-chip TDC using a Vernier delay line.