|کد مقاله||سال انتشار||مقاله انگلیسی||ترجمه فارسی||تعداد کلمات|
|140672||2018||18 صفحه PDF||سفارش دهید||6060 کلمه|
Publisher : Elsevier - Science Direct (الزویر - ساینس دایرکت)
Journal : AEU - International Journal of Electronics and Communications, Volume 83, January 2018, Pages 204-212
In this paper, a low power dynamic circuit is presented to reduce the power consumption of bit lines in multi-port memories. Using the proposed circuit, the voltage swing of the pull-down network is lowered to reduce the power consumption of wide fan-in gates employed in memoryâs bit lines. Wide fan-in OR gates are designed and simulated using the proposed dynamic circuit in 90Â nm CMOS technology. Simulation results show at least 40% reduction of power consumption and 1.2X noise immunity improvement compared to the conventional dynamic circuits at the same delay. Exploiting the proposed dynamic circuit, wide fan-in multiplexers are also designed. The multiplexers are simulated using a 90Â nm CMOS model in all process corners. The results show 41% power reduction and 27% speed improvement for the proposed 128-input multiplexer in comparison with the conventional multiplexer at the same noise immunity.