|کد مقاله||سال انتشار||مقاله انگلیسی||ترجمه فارسی||تعداد کلمات|
|140678||2018||11 صفحه PDF||سفارش دهید||5960 کلمه|
Publisher : Elsevier - Science Direct (الزویر - ساینس دایرکت)
Journal : Microelectronics Journal, Volume 74, April 2018, Pages 49-59
A novel full-swing, low-power and energy-aware full adder using hybrid logic scheme is presented in this paper. At first, a new energy-efficient 10T XOR-XNOR cell is designed by modifying inverter and pass transistor based 3T XOR-XNOR gates combined with a feedback loop. The performance of this new cell is compared with some reported ones and then, using this new cell and two other modules, a novel full adder circuit is proposed and evaluated in TSMC 0.18â¯Î¼m CMOS process technology. Post-layout simulations using Cadence Virtuoso tool showed 33%â74% and 35%â81% improvement in terms of power consumption and power-delay product (PDP), respectively, compared with some well-known counterparts in the literature. Furthermore, high-performance claim of our proposed full adder cell is verified through the process, voltage and temperature (PVT) variations' simulation of the adders. Finally, implementation of different full adders in 4-bit ripple carry adders (RCAs) proved our new design has high performance in the aspects of power dissipation and PDP.