دانلود مقاله ISI انگلیسی شماره 143988
کد مقاله سال انتشار مقاله انگلیسی ترجمه فارسی تعداد کلمات
143988 2018 9 صفحه PDF سفارش دهید 5874 کلمه
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عنوان انگلیسی
VLSI design and implementation of a reconfigurable hardware-friendly Polar encoder architecture for emerging high-speed 5G system
منبع

Publisher : Elsevier - Science Direct (الزویر - ساینس دایرکت)

Journal : Integration, Available online 27 March 2018

پیش نمایش مقاله
پیش نمایش مقاله

چکیده انگلیسی

In this paper, we propose a reconfigurable hardware-friendly VLSI architecture of the radix-2r based Polar encoder for emerging high-speed 5G system, including single-radix and reconfigurable multi-radix modes. In a single-radix structure, by using TSMC 90 nm CMOS technology, a 16384-point radix-2 based Polar encoder design is synthesized with 0.244 mm2 under maximum clock frequency of 2.0 GHz. In post-APR ASIC results, the radix-2 based Polar encoder only occupies 0.305 mm2 and consumes 357.8 mW at maximum clock frequency of 1.61 GHz. The VLSI hardware circuit can be extended to any radix-2r based design in a similar manner. In a reconfigurable multi-radix structure, a 4096-point 3-mode reconfigurable Polar encoder design is implemented with TSMC 90 nm CMOS technology, only owning a chip layout area of 0.13 mm2 and consuming 37.2, 32.0, and 26.2 mW in radix-2, radix-4, and radix-8 operating modes, respectively. The benefit of supporting different radix modes is to provide a design trade-off between power consumption and possible Polar encoder size selections.

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