|کد مقاله||سال انتشار||مقاله انگلیسی||ترجمه فارسی||تعداد کلمات|
|146248||2018||16 صفحه PDF||سفارش دهید||6890 کلمه|
Publisher : Elsevier - Science Direct (الزویر - ساینس دایرکت)
Journal : Microelectronics Journal, Volume 73, March 2018, Pages 59-74
This paper presents the design of a dual-output reconfigurable buck-boost switched capacitor converter architecture that can be adapted for applications requiring multiple, distributed on-chip loads. This system uses adaptive gain control and discrete frequency scaling to regulate power delivered. Core-interleaving, an enhanced load regulation scheme, and adaptive switch-sizing control have also been adopted to improve performance. The converter provides a fully-integrated, low-area and fully digital solution. Design and implementation using a standard bulk-CMOS 0.18â¯Âµm process provide simulation results showing that the converter has an output voltage range of 1.0â2.2â¯V, can deliver up to 7.5â¯mW of power to each load, and is up to 67% efficient, using an active area of only 0.06â¯mm2.