|کد مقاله||سال انتشار||مقاله انگلیسی||ترجمه فارسی||تعداد کلمات|
|148997||2017||14 صفحه PDF||سفارش دهید||6779 کلمه|
Publisher : Elsevier - Science Direct (الزویر - ساینس دایرکت)
Journal : Microprocessors and Microsystems, Volume 52, July 2017, Pages 287-298
Integrating reconfigurable fabrics in SOCs requires an accurate estimation of the layout area of the reconfigurable fabrics in order to properly optimize the architectural-level design of the fabrics and accommodate early floor-planning. This work examines the accuracy of using minimum width transistor area, a widely-used area model in many previous FPGA architectural studies, in accurately predicting layout area. In particular, the layout areas of LUT multiplexers are used as a case study. We found that compared to the minimum width transistor area, the traditional metal area based stick diagrams can provide much more accurate layout area estimations. In particular, minimum width transistor area can underestimate the layout area of LUT multiplexers by as much as a factor of 2â3 while stick diagrams can achieve over 90% accuracy in layout area estimation while remaining IC-process independent.