تست نیمه هادی مدل سازی برنامه ریزی شغلی و پیکربندی دستگاه تست پویا
|کد مقاله||سال انتشار||تعداد صفحات مقاله انگلیسی||ترجمه فارسی|
|20183||2008||12 صفحه PDF||سفارش دهید|
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Publisher : Elsevier - Science Direct (الزویر - ساینس دایرکت)
Journal : Expert Systems with Applications, Volume 35, Issues 1–2, July–August 2008, Pages 485–496
The overall flow of the final test of integrated circuits can be represented by the job shop model with limited simultaneous multiple resources in which various product mixes, jobs recirculation, uncertain arrival of jobs, and unstable processing times complicate the problem. Rather than relying on domain experts, this study aims to develop a hybrid approach including a mathematical programming model to optimize the testing job scheduling and an algorithm to specify the machine configuration of each job and allocate specific resources. Furthermore, a genetic algorithm is also developed to solve the problem in a short time for implementation. The results of detailed scheduling can be graphically represented as timetables of testing resources in Gantt charts. The empirical results demonstrated viability of the proposed approach.
The semiconductor industry has grown rapidly and subsequent production planning problems have raised many important research issues (Lee et al., 1992 and Leachman, 1993). The semiconductor companies compete with each other in cost structure, quality, and the delivery to maintain their competitive advantages (Chien, Wang, & Cheng, 2007). The semiconductor manufacturing scheduling problem is complicated by various product mixes, jobs recirculation, uncertain arrival of jobs, and unstable processing times. In particular, final testing of integrated circuits (IC) devices is the final operation in semiconductor manufacturing. The objectives of final test are to deliver passed IC devices of the required quality on time to customers while using resources efficiently. The overall flow of the final test can be represented by the job shop model with limited resources. Many optimization models or algorithms for short-term production planning at the shop floor level have been developed. However, the manufacturing environment of final test is unstable and uncertain. For example, the machine condition is uncertain affecting the yield rate and the throughput. Hence, the scheduling problem of final test is more complex than the conventional job shop scheduling problem. The testing site is typically the bottleneck of the final test operation because the equipment at the testing site is expensive and limited in amount. Also, final test directly suffers from the uncertain arrival of jobs from upstream, job recirculations, long job processing time, and long machine setup time. Engineers who rely on personal domain knowledge cannot find optimal machine configuration to respond to production needs rapidly and effectively. However, few studies have been done to address the present problem. Focusing on real settings, this study aims to develop a hybrid approach to address semiconductor final test scheduling problem (SFTSP). In particular, the following manufacturing characteristics are considered. Firstly, the machines in the semiconductor final test facility are indeed the combinations of specific testers, handlers, and accessories. Such resources are limited and scheduling approaches must take the resource constraint into account (Chen et al., 1995 and Chien and Chen, 2007a). Secondly, while different types of test machines (different combinations of resources) can process the test for a given product at different speeds (different utilization rates), one machine configuration may be able to perform tests on more than one type of products. In addition to determine the testing schedule, the problem assigning a specific test machine configuration to a test job, given the limited resources, remains. Thirdly, changeover between different machine configurations requires sequence-dependent setup time including the disassembly time for original configurations and the assembly time for new machine configurations. Certainly, the sequence-dependent setup time reduces the utilization of testing resources and a good schedule avoids unnecessary setups (Chien & Chen, 2007b). Fourthly, the recirculations of testing jobs should be considered to ensure practical viability of the proposed scheduling method (Chien & Wu, 2003). Fifthly, some jobs that are released late but with higher priority and should be delivered on time may interrupt the earlier schedule. Consequently, developing consistently well-performed algorithms for scheduling testing jobs is difficult. In this study, we developed a mathematical programming model to optimize the testing job scheduling and proposed an algorithm to specify the machine configuration of each job and allocate specific resources. Furthermore, a genetic algorithm is also developed to solve the problem in a short time for practical viability. The results of detailed scheduling can be graphically represented as timetables of testing resources in Gantt charts. For validation, the results of the proposed approach are then compared with those of existing models. The rest of this paper is organized as follows. Section 2 structures the semiconductor final test scheduling problem and reviews related research. Section 3 presents a mathematical model of job scheduling and the assignment algorithm to determine the machine configuration. Section 4 proposes a genetic algorithm to solve this problem. Section 5 compares the experimental results of the proposed model and genetic algorithm with those of existing studies. Conclusions and future research suggestions are finally made in Section 6.
نتیجه گیری انگلیسی
In this study, we developed a MILP model of the testing scheduling problem to determine the optimal schedule in which most important characteristics of SFTSP were considered. The proposed MILP comprised a number of details which have not been explicitly modeled in the literature so that optimality of the problem or the approximation of a proposed heuristic can be examined. Furthermore, an assignment algorithm was developed to determine the corresponding machine configurations and graphically show the optimal schedule in timetables. However, computer memory restriction and computation time limitation disabled the proposed model from generating an optimal schedule in real settings. Alternatively, a genetic algorithm (GASFTSP) minimizing the makepsan of the testing scheduling problem was proposed to reduce computation effort. The performance of GASFTSP was compared with the heuristics applying various single dispatching rules. After a number of simulation runs, GASFTSP was found consistently to outperform the other ruled-based heuristics with respect to the objective of minimizing makespan. Additionally, GASFTSP was shown to consistently obtain a near-optimal schedule within a reasonable computing time and with low costs to maintain. A decision support system (DSS) utilizing the proposed GASFTSP with a graphical user interface has been developed to assist the engineers in testing scheduling in an industrial-collaborative semiconductor final testing facility. Future research can be done to improve efficiency of the proposed GASFTSP. One possible direction would be incorporating several single dispatching rules as chromosomes into the initial population of GA instead of all randomly generating combinations of dispatching rules as chromosomes. On the other hand, investigating novel dispatching rules could also contribute to ease of computation. Moreover, the computing effort and solution quality of the genetic algorithm are greatly influenced by the factors including encoding and decoding methods, selection strategies, crossover and mutation operators, and crossover and mutation rates. With efficiency improvement, the proposed GASFTSP can possibly deal with dynamic job arrival problems. Consequently, schedulers can continuously run daily schedules and reschedule whenever a disruption occurs (Perry & Uzsoy, 1993). Continuously well-performed scheduling will increase long-term testing profit. In addition, further research should be done to develop effective indices to evaluate the performance of machine configurations (Chien, Chen, Wu, & Hu, 2007). Furthermore, it would be beneficial to examine the sensitivity of solution quality with respect to the availability of different accessories to see possible trade-offs between accessory purchase and productivity performance, e.g., makespan or total weighted tardiness.