دانلود مقاله ISI انگلیسی شماره 21893
عنوان فارسی مقاله

جریان کاری ریخته گری برای سطح شیب دار عملکرد مبتنی بر EFA پویا

کد مقاله سال انتشار مقاله انگلیسی ترجمه فارسی تعداد کلمات
21893 2011 5 صفحه PDF سفارش دهید محاسبه نشده
خرید مقاله
پس از پرداخت، فوراً می توانید مقاله را دانلود فرمایید.
عنوان انگلیسی
Foundry workflow for dynamic-EFA-based yield ramp
منبع

Publisher : Elsevier - Science Direct (الزویر - ساینس دایرکت)

Journal : Microelectronics Reliability, Volume 51, Issues 9–11, September–November 2011, Pages 1668–1672

کلمات کلیدی
- افزایش تقاضا - تجزیه و تحلیل شکست - جریان کاری ریخته گری
پیش نمایش مقاله
پیش نمایش مقاله جریان کاری ریخته گری برای سطح شیب دار عملکرد مبتنی بر EFA پویا

چکیده انگلیسی

The increasing demand for electrical failure analysis (EFA) in yield enhancement [1] has created new challenges for foundries and their clients. Dynamic EFA techniques, more in demand with the smaller technology nodes, have largely been the domain of the design-house failure analysis (FA) lab. In 2010 on 40 nm packaged parts, a new laser-based technology, laser voltage imaging (LVI) was applied to shift debug and drove physical failure analysis (PFA) success rate to >90%. This is still the case in 2011 on 28 nm ICs. The methodology was validated at the foundry on 32 nm wafers and again drove the PFA success rate to >90%. This paper offers a foundry-friendly methodology made possible by LVI and its fast track to the wafer level.

مقدمه انگلیسی

A surge in the number of defects discovered only at electrical test has created greater demand for dynamic EFA techniques. However, to make these techniques viable in yield operations, they must be foundry-friendly: 1. Dynamic EFA requires a tester. Any alterations to production test patterns would not be a viable solution for the foundry. 2. Dynamic EFA is more efficient when a region of interest can be identified in the GDS chip space. This “map” must be generated at the design house and shipped to the foundry in non-proprietary format. 3. Using Dynamic EFA in the high-throughput environment of the foundry requires less data exchanges and iterations with the design house. A growing interest in using broken scan chains to drive yield [2] and [3] was motivation for FA & design for test (DFT) teams to concentrate on an EFA-based shift debug project. The first EFA technique, based on photon emission and good die/bad die comparisons, produced results that were difficult to interpret [4]. The second EFA technique, LVI, effectively isolated the fault to one or two flops plus connected nets, and often times provided additional insight into possible defect types [4] and [5]. This LVI/shift debug application has been reported to yield >90% PFA success for the die that were analyzed, both at package-level in an FA lab and at wafer-level in a foundry.

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