حساسیت کرنش نشتی دروازه در SOI nMOSFETs-فشرده شده : سود برای عملکرد تجارت کردن و راه جدیدی را برای استخراج فشار-القایی انحراف نوار
|کد مقاله||سال انتشار||مقاله انگلیسی||ترجمه فارسی||تعداد کلمات|
|22954||2009||4 صفحه PDF||سفارش دهید||2874 کلمه|
Publisher : Elsevier - Science Direct (الزویر - ساینس دایرکت)
Journal : Microelectronic Engineering, Volume 86, Issues 7–9, July–September 2009, Pages 1897–1900
The impact of biaxial stress on gate leakage is investigated on fully-depleted silicon-on-insulator (FD-SOI) nMOS transistors, integrating either a standard gate stack or an advanced high-κ/metal gate stack. It is demonstrated that strained devices exhibit significantly reduced leakage currents (up to −90% at Eox = 11 MV/cm for σtensile = 2.5 GPa). This specific effect is used to extract the conduction band offset ΔEc induced by strain and is shown to be accurate enough to monitor stress in MOSFETs. This new technique is much less sensitive to gate oxide defects than the method based on the threshold voltage shift ΔVT. This accurate experimental extraction allowed us to pick out realistic values for the deformation potentials in silicon (Ξu = 8.5 eV and Ξd = −5.2 eV), among the published values.
Strained silicon films have been recently introduced in CMOS technologies to boost mobility performance of metal–oxide–semiconductor field-effect-transistors ,  and . The modification of the silicon band structure induced by biaxial strain also affects the threshold voltage Vt  and  and the gate leakage current density Jg , , ,  and , which has strong implication on circuit performance by reducing power consumption. Although accurate knowledge of the deformation potential values would be useful for modelling tools, there is still no consensus about their exact values, as shown by the various set of parameters found in the literature ,  and  (see inset of Fig. 3). In this paper, we propose to use the strain sensitivity of gate leakage to give realistic parameters. Results are compared to those obtained from an extraction based on the Vt shift, ΔVT.
نتیجه گیری انگلیسی
The effects of biaxial stress on electron mobility μe, threshold voltage Vt and gate current density Jg have been investigated. Two techniques, using either ΔVt extraction from Id(Vg) or Δϕb extraction from Ig(Vg) measurements, have been used to model the strain-induced band offset ΔEc. However the main advantage of Ig(Vg) measurements is that it is less sensitive to interface states or charged defects in the oxide. Finally, with tensile biaxial stress, we measured reduced gate leakage currents for both SiO2/poly-Si (EOT = 5 nm) and HfZrO/TiN (EOT = 1.3 nm) advanced gate stack.