طرح های FPGA برای به حداقل رساندن قدرت در استفاده از تجارت کردن در اجرای الگوریتم استاندارد رمزگذاری پیشرفته
|کد مقاله||سال انتشار||مقاله انگلیسی||ترجمه فارسی||تعداد کلمات|
|23736||2010||8 صفحه PDF||سفارش دهید||محاسبه نشده|
Publisher : Elsevier - Science Direct (الزویر - ساینس دایرکت)
Journal : Journal of Systems Architecture, Volume 56, Issues 2–3, February–March 2010, Pages 116–123
Today most research involving the execution of the Advanced Encryption Standard (AES) algorithm falls into three areas: ultra-high-speed encryption, very low power consumption, and algorithmic integrity. This study’s focus is on how to lower the power consumption of an FPGA-based encryption scheme with minimum effect on performance. Three novel FPGA schemes are introduced and evaluated. These schemes are compared in terms of architectural and performance differences, as well as the power consumption rates. The results show that the proposed schemes are able to reduce the logic and signal power by 60% and 27%, respectively on a Virtex 2 Pro FPGA while maintaining a high level of throughput.
Communication among a large number and diverse set of devices has increased dramatically in recent years. This in turn has led not only to the need for connecting a large number of devices, but means to ensure that communication is secure. Today the most commonly used and accepted standard for private key encryption is the Advanced Encryption Standard (AES). Since its inception AES has been the subject of in-depth research that has typically focused on three areas. The first is algorithmic integrity, which ensures there is no feasible way to obtain the original data in a timely manner . The second area is high throughput schemes, which seek to carry out encryption as quickly as possible  and . The final area of emphasis has been on low power systems, which seek to minimize power consumption at all costs  and . Recently a combination of the latter two areas of research have become of great importance, allowing new implementations to maintain a high throughput while using as little hardware and power as possible. This area is growing increasingly important as devices are not only communicating in higher frequency, but in larger quantities and need to translate the secured data into a usable state as efficiently as possible. It is this research emphasis that this study explores. More specifically this study focuses on the implementations pertaining to FPGAs and reconfigurable hardware for the implementation of the AES algorithm. The primary reason for this is that as reconfigurable hardware technologies continue to progress it is becoming more viable for devices to use a single chip for multiple tasks and simply reconfigure the chip for its current need. This is particularly useful in the field of sensor networks where hardware and power is limited, but secure communications may be critical. This paper is organized as follows: Section 2 provides a brief overview of the AES algorithm. In Section 3 a brief description of current schemes is presented. Section 4 introduces the proposed schemes. In Section 5 a comparative analysis of the schemes is presented, the first half focuses on how the decisions made in a given scheme affected their performance and hardware requirements. The second half focuses on the power consumption of the schemes available for testing and what can be learned about how to control power consumption. Some concluding remarks are included in Section 6.
نتیجه گیری انگلیسی
In this paper three novel schemes have been presented; these schemes reduce the power consumption for a full 128 bit AES encryption device without dramatically affecting performance. A discussion of the architectural differences between the proposed and reference designs have been presented, focusing on the feature set and size requirement of each approach. The cost of using FPGAs has been also identified, which is the high quiescent power. Below, the contributions of this paper are outlined. • Comparison of DOR and DOR + K scheme performance to footprint size: through this analysis of the schemes it is apparent that the proposed DOR and DOR + K schemes outperform the reference schemes and those included in . The Gaj scheme from  is the closest of the reference schemes to the proposed schemes in the throughput/slice metric, but yielded a 20% lower throughput/slice result. Similarly if only throughput is considered the DOR + K design is not the fastest, but trails the highest throughput scheme by Dandalis et al. by only 0.93%, while using less than half of the required slices for implementation. • Low latency architecture: in an environment where time to complete an encryption is important such as sensor networks and time sensitive communications latency must be kept to a minimum, this task is particularly well suited to the proposed and reference schemes’ architectures and their choice not to depend on a given FPGAs memory architecture. The typical latency of all the proposed and reference schemes is 11 cycles with the cyphertext being available on that eleventh cycle. While some memory-based schemes such as Weaver  are able to maintain a competitive latency most memory schemes tend to ignore this metric due to high latency levels similar to McMillan 44 cycle latency . • Scheme partitioning and FPGA choice: through the comparative power analyses it is shown that proper attention must be paid to partitioning a design to ensure that power is not being consumed by unwarranted segments of a design. This is evident by comparing the DOR + K design to the Open Core design, since both schemes use similar architectures but the DOR + K requires 41.3% less power. Along with this it must also be stressed that FPGA choice is critical, because the majority of power consumed in the analyses was due to quiescent power. Using these two observations it can be shown that an FPGA must be chosen for how it best fits the chosen architecture of the scheme and not just because it has the lowest power requirements or the best resource utilization. An example would be to use a larger than necessary chip if it lowers the quiescent power for a high latency scheme or use a smaller chip with marginally higher power requirements for a low latency space restricted scheme. • Power reduction with increased performance: the proposed DOR and DOR + K schemes are able to operate at higher clock frequencies than the reference schemes. DOR and DOR + K, operating at the same clock rates, are able to reduce the logic and signal power requirements by as much as 41% and 27%. Furthermore the designs could be implemented on newer FPGAs for even greater performance improvements without having to consider BRAM constraints.