دانلود مقاله ISI انگلیسی شماره 52426
عنوان فارسی مقاله

یک چارچوب جدید برای زمان بندی دوباره با استفاده از محاسبات تکاملی برای سنتز سطح بالایی از فیلتر های دیجیتال

کد مقاله سال انتشار مقاله انگلیسی ترجمه فارسی تعداد کلمات
52426 2015 11 صفحه PDF سفارش دهید محاسبه نشده
خرید مقاله
پس از پرداخت، فوراً می توانید مقاله را دانلود فرمایید.
عنوان انگلیسی
A novel framework for retiming using evolutionary computation for high level synthesis of digital filters
منبع

Publisher : Elsevier - Science Direct (الزویر - ساینس دایرکت)

Journal : Swarm and Evolutionary Computation, Volume 20, February 2015, Pages 37–47

کلمات کلیدی
فضای جواب؛ انتخاب مسابقه؛ بهینه سازی فیلتر دیجیتال؛ زمان بندی دوباره - نمودار جریان داده ها؛
پیش نمایش مقاله
پیش نمایش مقاله یک چارچوب جدید برای زمان بندی دوباره با استفاده از محاسبات تکاملی برای سنتز سطح بالایی از فیلتر های دیجیتال

چکیده انگلیسی

In this paper, design of a new algorithm and a framework for retiming the DSP blocks based on evolutionary computation process is explained. Optimal DSP blocks such as digital filter design is a high level synthesis problem which includes optimally mapping digital filter specifications on to FPGA (Field Programmable Gate Array) architecture. Retiming is the considered optimization method in this paper which gives optimality in terms of algorithm processing speed and digital filter operating frequency with register count as a constraint. The designed novel algorithm is for the synthesis of high speed digital filters for different signal processing applications based on nature inspired evolutionary computation method. The classical retiming algorithms such as clock period minimization and register minimization that are addressed in the literature provide a single heuristic solution based on the chosen optimization parameter such as clock period. However, for retiming which is multi-objective optimization, evolutionary approach can lead to better results. Using the designed evolutionary computation based retiming method, retimed solution database is generated with higher frequency and different output register counts by searching the digital block solution space. Depending on the clock period and register count constraint, designer can take a design decision. Here, various signal processing designs are used to facilitate the design analysis. Results also show that the CPU processing time needed to compute multiple solutions using the designed algorithm for filter circuits is reduced for designs whose maximum feasible solutions are less than 50. If the circuit is very big with the possible solution space greater than 50 solutions, then algorithm performs slower. A comparison is also provided in the Simulations section with respect to all the existing classical retiming methods in the literature such as clock period and register minimization retiming to prove the concept. Multi-objective genetic algorithms are the considered evolutionary computation method in this paper.

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