کاهش تلفات خط انتقال با استفاده از اتصالی VLSI
|کد مقاله||سال انتشار||مقاله انگلیسی||ترجمه فارسی||تعداد کلمات|
|54560||2012||10 صفحه PDF||سفارش دهید||3375 کلمه|
Publisher : Elsevier - Science Direct (الزویر - ساینس دایرکت)
Journal : Procedia Engineering, Volume 30, 2012, Pages 10–19
60-70% of the power generated is lost during transmission and distribution phase. Out of this maximum losses occur at transmission and distribution line interconnects, which comprises 40 to 50% of the total loss. To reduce this scientist have come up with an idea of using VLSI interconnects. We analyzed various methods of R-L-C interconnect used currently and losses that take place due to them. Further in our study CMOS interconnects were implemented in the same circuit and their results were analyzed. Traditionally, the total delay (i.e., latency) of a circuit is considered to measure its performance. The total delay comprises of two components, the transistor delay and the interconnect delay. Interconnect delay, which was once considered to be quite insignificant has become a major problem with the growing worldwide network. While trying to find economical, practically feasible and implementable method for reduction of transmission line losses, we did real time simulation of various combinations of CMOS circuit of a transmission line model and studied its characteristic. The variation in characteristic with respect to time gave a preview of effect of change of various configuration of passive element with CMOS design circuit. The effect of crosstalk was also analyzed.