تحلیل نشت کامل تراشه برای فن آوری CMOS شصت و پنج نانومتری و فراتر از آن
|کد مقاله||سال انتشار||مقاله انگلیسی||ترجمه فارسی||تعداد کلمات|
|56122||2010||12 صفحه PDF||سفارش دهید||محاسبه نشده|
Publisher : Elsevier - Science Direct (الزویر - ساینس دایرکت)
Journal : Integration, the VLSI Journal, Volume 43, Issue 4, September 2010, Pages 353–364
This work proposes a full-chip leakage analysis framework for 65 nm technology and beyond. Analytical models are first constructed to capture the impact of process parameters on leakage current. Then a methodology is introduced to characterize leakage-related process variations in a systematic manner. On such a basis, an efficient procedure is developed to analyze the state-dependent power dissipation due to leakage of a large circuit block by taking into account different leakage mechanisms. Unlike many traditional approaches that rely on log-normal approximations, the proposed algorithm applies a quadratic model of the logarithm for the full-chip leakage current. It is able to handle both Gaussian and non-Gaussian parameter distributions. The model is validated with test chips manufactured with a commercial 65 nm CMOS process. Validation results prove that the proposed modeling methodology could achieve a higher accuracy than that from existing methods. Moreover, a full-chip leakage analysis using the developed model can be orders of magnitude faster than a Monte Carlo based approach.