دانلود مقاله ISI انگلیسی شماره 62977
ترجمه فارسی عنوان مقاله

اکتشاف چندهدفه کارآمد فضای طراحی و ترکیب معماری پردازنده خاص کاربردی (ASP)

عنوان انگلیسی
Multi-objective efficient design space exploration and architectural synthesis of an application specific processor (ASP)
کد مقاله سال انتشار تعداد صفحات مقاله انگلیسی
62977 2011 13 صفحه PDF
منبع

Publisher : Elsevier - Science Direct (الزویر - ساینس دایرکت)

Journal : Microprocessors and Microsystems, Volume 35, Issue 4, June 2011, Pages 392–404

ترجمه کلمات کلیدی
پردازنده خاص برنامه کاربردی؛ اکتشافات فضایی طراحی؛ چند هدفه؛ محدودیت های عملیاتی مرکب؛ RTL
کلمات کلیدی انگلیسی
Application specific processor; Design space exploration; Multi-objective; Compound operational constraints; RTL
پیش نمایش مقاله
پیش نمایش مقاله  اکتشاف چندهدفه کارآمد فضای طراحی و ترکیب معماری پردازنده خاص کاربردی (ASP)

چکیده انگلیسی

As the growth of system complexity rapidly increases, the gap between Electronic System Level (ESL) and the Register Transfer Level (RTL) must be filled. Currently, Very Large Scale Integration (VLSI) and System-on-Chip (SoC) designs are multi-objective in nature, requiring simultaneous fulfillment of multiple parameters. Extensive research on Design Space Exploration (DSE) problems and synthesis of an application specific processor (ASP) design have been done until now but none of the prior works have focused explicitly on integrating a fast multi-objective architecture exploration mechanism with the architectural synthesis stages to formalize the design methodology of an application specific processor in case of multiple objectives. This paper proposes a design methodology of a multi-objective application specific processor by integrating an efficient multi-objective (area occupied, execution time and power consumption) exploration approach with the architecture synthesis process, useful for portable devices and many high end applications. The formalized steps of the design methodology for the ASP guarantees the designer an error free approach to design the system with strict limitations on compound operational constraints. The results of implementation of the designed ASP using the proposed design methodology in FPGA and ASIC have also been shown.