تکنیک تنظیم انبارهای دو سطحی برای مصرف انرژی در تنظیم مجدد MPSoC تعبیه شده
|کد مقاله||سال انتشار||مقاله انگلیسی||ترجمه فارسی||تعداد کلمات|
|6361||2013||12 صفحه PDF||سفارش دهید||محاسبه نشده|
Publisher : Elsevier - Science Direct (الزویر - ساینس دایرکت)
Journal : Journal of Systems Architecture, Available online 5 June 2013
In order to meet the ever-increasing computing requirement in the embedded market, multiprocessor chips were proposed as the best way out. In this work we investigate the energy consumption in these embedded MPSoC systems. One of the efficient solutions to reduce the energy consumption is to reconfigure the cache memories. This approach was applied for one cache level /one processor architecture, but has not yet been investigated for multiprocessor architecture with two level caches. The main contribution of this paper is to explore two level caches (L1/L2) multiprocessor architecture by estimating the energy consumption. Using a simulation platform, we first built a multiprocessor architecture, and then we propose a new algorithm that tunes the two-level cache memory hierarchy (L1 & L2). The tuning caches approach is based on three parameters: cache size, line size, and associativity. To find the best cache configuration, the application is divided into several execution intervals. And then, for each interval, we generate the best cache configuration; Finally, the approach is validated using a set of open source benchmarks; Spec2006, Splash-2, MediaBench and we discuss the performance in terms of speedup and energy reduction.
In order to meet the ever-increasing computing requirement in the embedded market, and in particular multimedia market; multiprocessor chips (MPSoC – Multiprocessor System on Chip) were proposed as the best way out. Game consoles and smart-phones are a typical example of these embedded MPSoC systems. Several functionalities are integrated in such systems (e.g. voice communication, audio–video encoding, web browsing, exchange message, gaming, etc.). Thus, those functionalities need for a long lifetime battery and an effective power management on-chip technique. In order to fill the gap between the CPUs speed and the global memory system, MPSoC architectures implements hierarchical memory structures (or caches). These memory hierarchies contribute largely in the energy consumption of the overall hardware/software architecture. Multilevel caches are responsible for a significant part. Over 50% of the total energy consumption system is due to its large on-chip area and high access frequency  and . Customizing the memory hierarchy for a given application by reconfiguring the caches dynamically is being introduced as an efficient solution to save energy use in many processors based architectures. On the other hand a cache is organized by three parameters: the cache size (s), the cache line size (l), and the cache associativity (a). Tuning the three cache parameters during the execution time to find the best cache configuration for a software task may considerably save the whole energy consumption of the system. Dynamic cache reconfiguration has been well studied for single processor in both general-purpose computers as well as real-time embedded systems , , , ,  and . Typically, L2 cache acts as a shared resource in MPSoC. Recent research has shown that shared on-chip cache may become a performance bottleneck for MPSoC because of contentions among parallel running tasks ,  and .
نتیجه گیری انگلیسی
In this paper we evaluate the energy consumption in embedded MPSoC system using cache-tuning approach. It concerns two level caches (L1/L2) in multiprocessor architecture. The cache tuning was applied for one processor based architecture with one cache level, but has not yet been studied for multiprocessor architecture with two level caches. We propose an efficient solution to reduce the energy use in cache memories. The proposed solution is based on tuning the cache memories for a given application that have been divided into several intervals. The tuning is based on three parameters: cache size, line size, and associativity. In the proposed framework, the ICTT reconfiguration algorithm took into account two types of applications, with constant instructions, and data-flow. In the first one, the heuristic explores and locates the best cache configuration for each interval in term of energy saves, and generates automatically the best cache configuration parameters for each interval of the application. In that way the total energy consumption for a given application is reduced. But for applications with continued data-stream, the reconfiguration decision is taken with incomplete information about the upcoming data. In that case, the ICTT heuristic accomplishes the cache reconfiguration in a different way. Therefore, the cache reconfiguration is done just for a defined number of iterations and then we force the heuristic to converge and get the best cache configuration for given interval. This configuration is used for the rest of the execution time of the application. Finally, the approach was validated using several benchmarks and we discuss the performance in terms of energy reduction. We have also to mention that the heuristic is more suitable for an application with variable tuning. And more appropriate if we need a rapid exploration to get a solution near to optimal for our architecture design.