دانلود مقاله ISI انگلیسی شماره 8244
عنوان فارسی مقاله

بهینه سازی سریع نانو و ولتاژ کنترل اسیلاتور با استفاده از رگرسیون چند جمله ای و الگوریتم ژنتیک

کد مقاله سال انتشار مقاله انگلیسی ترجمه فارسی تعداد کلمات
8244 2013 11 صفحه PDF سفارش دهید محاسبه نشده
خرید مقاله
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عنوان انگلیسی
Fast optimization of nano-CMOS voltage-controlled oscillator using polynomial regression and genetic algorithm
منبع

Publisher : Elsevier - Science Direct (الزویر - ساینس دایرکت)

Journal : Microelectronics Journal, Volume 44, Issue 8, August 2013, Pages 631–641

کلمات کلیدی
بهینه سازی مدار - بهینه سازی طراحی - رگرسیون چند جمله ای - الگوریتم ژنتیک
پیش نمایش مقاله
پیش نمایش مقاله بهینه سازی سریع نانو و ولتاژ کنترل اسیلاتور با استفاده از رگرسیون چند جمله ای و الگوریتم ژنتیک

چکیده انگلیسی

Fast optimization of CMOS circuits is needed to reduce design cycle time and chip cost and to enhance yield. Mature electronic design automation (EDA) tools and well-defined abstraction-levels for digital circuits have largely automated the digital design process. However, analog circuit design and optimization is still not automated. Custom design of analog circuits and slow analog in SPICE has always needed maximum efforts, skills and design cycle time. In this paper, two novel design flows are presented for fast multiobjective optimization of nano-CMOS circuits: actual-value optimization and normalized-value optimization. The design flows consider two characteristics for optimization i.e. power and frequency in a current-starved 50 nm voltage-controlled oscillator (VCO). Accurate polynomial-regression based models have been developed for power (including leakage) and frequency of the VCO to speedup the design optimization. In the actual-value optimization flow, the power model is minimized using genetic algorithm, while treating frequency View the MathML source≥100MHz as a constraint. The actual-value optimization flow achieved 21.67% power savings, while maintaining a frequency View the MathML source≥100MHz. In the normalized-value optimization flow, the normalized form of these models are subjected to a weighted optimization using genetic algorithm. The normalized-value optimization flow achieved 16.67% power savings, with frequency View the MathML source≥100MHz. It is observed that while the actual-value optimization approach provides a better exploration of the design space, the normalized-value optimization approach provides a ≈5×≈5× speedup in the computation time

مقدمه انگلیسی

Digital design exploration and optimization is highly automated due to availability of large number of electronic design automation (EDA) or computer-aided design (CAD) tools. The digital design automation is aided by the availability of well-defined abstractions for digital circuits (such as system, architecture, and logic levels). However, analog design optimization is still a difficult and time intensive process [1]. For example, the analog simulation time for a nano-CMOS phase-locked loop is a matter of several days. So, debugging such a design is time intensive and costly. This results in high-cost and longer design cycle time. If such analog design are performed at nano-CMOS technology, the issues are further complicated due to leakage and process variation resulting in yield loss. Most analog integrated circuit (IC) optimization problems involve minimizing a cost function subject to certain constraints. Due to the increasing complexity of modern analog integrated circuits, analog sizing has evolved into a “simulation and optimization” based approach from a “paper and pencil” based approach [2]. Analog sizing problems often require handling multiple conflicting goals, such as power consumption and frequency of a VCO [3]. Novel design/optimization flows are needed, to help the circuit designers [4]. Multi-objective optimization [5] is the process of simultaneously optimizing two or more conflicting design objectives while subjecting the design variables to constraints. During optimization, the baseline design is iteratively tuned by adjusting a large number of design parameters to vast amounts of different design possibilities of the circuit to meet the target design objectives, making it very tedious to do exhaustive design space exploration for complex nano-CMOS circuits to find an optimal solution. Also, the use of compact models [6] with hundreds of parameters in nano-CMOS technology further aggravates the situation. Polynomial regression model is an abstract model of the netlist which enables a fast design space search. Polynomial regression models are useful for relative functions to unknown and very complex non-linear relationship [7] and [8]. This model is a mathematical predictive equation which may be used as a substitute for the actual circuit, leading to easier and faster simulations with multiple iterations during optimization. For example, as reported in current literature, simulated annealing used on a circuit netlist in a simulator gives convergence in order of minutes as compared to milliseconds, when used over a polynomial regression model [9]. Hence, it can be used as an alternative to the exhaustive search of the design space of the actual circuits. The model can also be used in a variety of tools, such as MATLAB, and is language independent and can be used in a flexible fashion. To give an overview, the notations and definitions for various terminologies used in this paper are given in Table 1. The paper is organized in the following manner: Contributions of this paper are summarized in Section 2. Section 3 presents the prior related research. Section 4 discusses the proposed novel design flows. The design and analysis of the 50 nm VCO is presented in Section 5. Polynomial models for actual-value and normalized-value optimization are presented in Sections 6 and 7, respectively. Sections 8 and 9 highlight the optimization step of the optimization flows, using genetic algorithm. This is followed by conclusions and future research in Section 10.

نتیجه گیری انگلیسی

We have presented two design flows for polynomial regression model assisted multiobjective optimization on a 50 nm CMOS based VCO. The center frequency and power dissipation have been considered for optimization. A model-based approach is beneficial as it is faster than optimizing the actual circuit. The proposed approach leads to 21.67% power reduction for actual-value optimization (which converges in 2.99 s) and 16.67% power savings for normalized-value optimization, which converges in 0.6 s. The error introduced by the model based approach is very minimal which is in the range of 0.1–4.0%. Thus, the proposed research is a significant advancement of the state-of-art in the analog design optimization. The proposed research will help to reduce the design cycle time and reduce the chip cost. As part of future research, regression based models will be developed, taking into account supply sensitivity, temperature sensitivity and parasitics. One possible way to study PVT variations effect on the VCO could be to develop polynomial regression models for the VCO while subjecting it to worst case process and temperature corner. These regression models may then be optimized for the worst case process, which will work well for the nominal corner. Takagi–Sugeno neuro-fuzzy logic systems will also be explored for modeling. VCO performance parameters other than power and frequency, such as phase noise, tuning linearity will also be considered. Also, the actual-value optimization problem presented in this paper will be solved using other algorithms such as the Lagrange multiplier method and artificial bee colony. The effects of process variation will be incorporated in future statistical design flows.

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