رویکرد ODYSSEY برای بررسی اولیه هم ارزی مبتنی بر شبیه سازی در سطح سیستم های الکترونیکی با استفاده از تولید خودکار مدل های اجرایی در سطح معامله
|کد مقاله||سال انتشار||مقاله انگلیسی||ترجمه فارسی||تعداد کلمات|
|9217||2008||11 صفحه PDF||سفارش دهید||محاسبه نشده|
Publisher : Elsevier - Science Direct (الزویر - ساینس دایرکت)
Journal : Microprocessors and Microsystems, Volume 32, Issue 7, October 2008, Pages 364–374
Design technology is expected to rise to electronic system-level (ESL). This necessitates new techniques and tools for synthesizing ESL designs and for verifying them before and after ESL synthesis. A promising verification strategy for future very complex designs is to initially verify the design at the highest level of abstraction, and then check the equivalence of the lower level automatically generated models against that initial golden model. We present one such approach to simulation-based functional verification implemented in our ESL design methodology called ODYSSEY. Our ESL synthesis tool generates a transaction-level model (TLM) at TLM level 2 (i.e., design with partial timing) that corresponds to the input ESL design (which is at TLM level 3; i.e., sole functionality without timing). Both the ESL design and its generated TLM model can be simulated on a host machine with corresponding input stimuli to establish their functional equivalence. The TLM is in SystemC, and hence executable, and also models both hardware and software components in C++ to achieve higher simulation speed. We introduce an implementation of a TLM level 2 model that is tailored to our ESL design methodology and apply our approach to a number of benchmarks to evaluate the TLM simulation performance. Experimental results show that the approach suits early validation of the ESL synthesis process since its simulation performance is more than 4 orders of magnitude higher than simulations at lower levels and it is generated early in the design cycle. Also the co-simulation overhead – compared to simulating the original ESL design in C++ – depends on the partitioning quality in terms of communication to computation ratio.
Starting the design from higher levels of abstraction is inevitable to excel the designers’ productivity . The industry trend has already been toward electronic system-level (ESL) design , where software and hardware of the system are co-designed. In such a design flow, the design process starts from an implementation-independent system model that is later partitioned and elaborated to hardware and software components. This elaboration/partitioning, which we hereafter refer to as ESL synthesis, is an essential part of ESL design, and furthermore, is difficult to verify since the pre- and post-synthesis models are in different semantic domains; the pre-synthesis model is implementation-independent whereas the post-synthesis model is a heterogeneous combination of sequential functional software and parallel structural hardware. In this paper we present our approach to tackle this problem in ODYSSEY project . The International Technology Roadmap for Semiconductors (ITRS) suggests that future design technologies should facilitate verification of the system-under-design much earlier in the design flow to avoid costly design iterations from lower levels . Fig. 1 shows past, present, and envisioned future design system architectures as viewed by ITRS. In the past (left hand side of the figure), only the operations from register transfer level (RTL) design down to the final implementation employed equivalence checking (look at the EQ Check rectangle at the bottom left of the figure) while various tools and multiple design files were generated and used for hardware synthesis; hardware/software partitioning and optimization were also manual tasks accomplished by expert system designers (look at HW/SW optimization cloud at middle left of Fig. 1), and moreover, software optimization was a separate process from hardware optimization procedure (see the separate SW opt box at left-middle of Fig. 1). At present (middle part of the figure), hardware/software partitioned model is generated from the high-level system model (compare the top parts of past and present in the figure) which enables some degree of design-space exploration; furthermore in the hardware optimization process, multiple design files are converged into one efficient data model that removes many tool interoperability issues and enables efficient iterative optimization methodologies during optimizations from RTL level down to the final implementation (look at the bottom-middle of Fig. 1 and compare it to the past case). In future (right hand side of the figure), software optimization and hardware/software partitioning and optimization are to be combined with hardware optimization process (look at the bottom of the flow) and more importantly, verification tasks all move to earlier, higher levels of abstraction (look at the box labeled “functional, performance, testability verification” at the top-right of Fig. 1) followed by equivalence checking and assertion-driven design optimization (see the third bullet in the text box at bottom-right of Fig. 1). In other words, this vision of ITRS suggests  that with the technology move to higher abstraction levels, modern equivalents are sought for the equivalence checking process that is currently done at logic and register transfer level (RTL).
نتیجه گیری انگلیسی
We presented an executable co-simulation TLM model and the simulation-based ESL verification procedure that we pursue in our ESL design methodology. The main thrusts of this paper are firstly to propose and implement a simulation-based equivalence checking strategy at ESL level that follows the guidelines that ITRS envisions for future design technology, secondly to introduce an automatically generated executable hardware–software transaction-level model tailored to our ESL design methodology, and finally to demonstrate that the partitioning quality (in terms of communication to computation ratio) determines the co-simulation performance, and hence, the co-simulation overhead can be an early indicator of the quality of the final implementation. Moreover, mechanical test-bench transformation capability of our synthesizer allows the user to more intensively verify the TLM model before further elaborating the design into the gate-level hardware and binary-code software. This prevents costly and time-consuming design iterations from lower level synthesis steps that could have become necessary due to undetected hardware–software inconsistencies or faults in the ESL synthesizer. Such a verification strategy proved essential when developing our design-automation tools  as well as when developing our real-world case studies . Envisioned future work includes exploring automatic hardware–software partitioning techniques so as to optimize certain quality metrics such as performance, power consumption, or system cost.