یک رویکرد سیستماتیک برای راستی آزمایی کاربردی قابل تنظیم بلوک های HW IP در سطح معامله
|کد مقاله||سال انتشار||مقاله انگلیسی||ترجمه فارسی||تعداد کلمات|
|9499||2012||11 صفحه PDF||سفارش دهید||محاسبه نشده|
Publisher : Elsevier - Science Direct (الزویر - ساینس دایرکت)
Journal : Computers & Electrical Engineering, Volume 38, Issue 6, November 2012, Pages 1513–1523
With demand growing by the day, the complexity of electronic devices is constantly increasing. Since simulation is still the most used approach, functional verification has become one of the major bottlenecks in the design and verification flow. In this paper we propose a systematic approach to configurable functional verification of electronic devices. Based on a black box approach, it can be applied to any design where behavior can be expressed by a set of functions. It combines simulation- and assertion-based verification into a hybrid verification. The proposed specification-based coverage metric can be configured ranging from a very rapid to an exhaustive verification. The approach uses Transaction Level (TL) modeling to raise the abstraction level, providing faster verification. The results of the proposed design and verification flow, Intellectual Property (IP) and Test Bench (TB) are reusable. The approach is demonstrated on two case-studies; a video-processing IP block and universal serial bus host controller. The results consider both simulation times and TB generation times.
Even though electronic devices already combine many different functions, the market continuously demands new functionality. In the future, the functionality of electronic devices will only need to be enhanced, meaning that their complexity will increase drastically, requiring more effort in the design and verification process. Simulation is still the most used approach to functional verification even though new verification techniques have been developed. However, due to the increased complexity of electronic devices, verification can take up to 80% of the device design time and cost when using Register Transfer Level (RTL) and Hardware (HW) models for simulation (,  and ). Considering the extreme time-to-market pressures, there is no doubt that advanced new solutions will have to be provided. One possible solution is in raising the level of abstraction. This approach has been successful in the past (transistor level → gate level → RTL). Raising the level of abstraction to Transaction Level Modeling (TLM) and using SystemC () to describe the models can provide many benefits. Device behavior can be expressed using high-level functions and high-level data types can be used for communication. The details of device architecture are omitted, allowing for a simpler and faster device model. This also permits a highly systematic approach to device modeling and verification. The designer is allowed to focus on the functionality first and on the implementation second. As a consequence, the verification process is also divided into stages. In the first stage, the high-level functional model is verified. Errors in the functional model that are propagated to the RTL level, or even to the gate level are very costly to repair in terms of time and money. So it is crucial to find and fix these errors in the early phases of the design and verification process. In the following stage, the RTL model is verified, with more emphasis placed on implementation of the verified functionality. Additional improvement can be achieved by combining formal Assertion-Based Verification (ABV) with Simulation-Based Verification (SBV), resulting in a hybrid verification. Assertions are a set of formal rules defined by the designer that are checked during the simulation. Assertions can help pinpoint an error in the design and find errors that would otherwise be very difficult to detect. The models used in this paper are described using SystemC. SystemC allows the HW description in C++, which is the basis for SW/HW co-verification. Therefore, verified functionality can be implemented either in SW or HW. A key concept in modern digital design is design reuse (). Modeling the device with functional blocks and verifying each block individually allows the designer to construct a database of verified blocks for future use. The Test Bench (TB), constructed for functional verification, can be reused for verification at lower levels of abstraction with the help of translators. The reuse of verified IP blocks and TB results allows for a considerable savings in time and cost.
نتیجه گیری انگلیسی
In this paper, we proposed a systematic approach to configurable functional verification at the TLM level. The hybrid verification used in our design and verification flow combines SBV and ABV. We showed that by using the black box approach it is possible to model any electronic device whose functionality can be expressed as a list of functions of high-level variables. We clearly demonstrated this on two very different case-studies. We showed how easy it is to configure a specification-based FCM ranging from a rapid to an exhaustive verification just by defining the variable divisors. We also established that an exhaustive verification of modern systems is very time-consuming and is therefore often not practical. The proposed approach can be used more than once in the design and verification flow process. In the early phases of development, the designer can use a fast verification on more than one occasion, while an exhaustive verification can be run at the end of the design process. The TB can also be reused on the RTL model with the use of a transactor. When designing an electronic system, we propose to construct it by combining a set of pre-verified IP blocks modeled and verified by using our approach.