Space missions require extremely high reliable components that must guarantee correct functionality without incurring in catastrophic effects. When electronic devices are adopted in space applications, radiation hardened technology should be mandatorily adopted. In this paper we propose a novel method for analyzing the sensitivity with respect to Single Event Latch-up (SEL) in radiation hardened technology. Experimental results obtained comparing heavy-ion beam campaign demonstrated the feasibility of the proposed solution.
Single Event Effects (SEEs) is a widely known phenomenon that leads to permanent or temporary damage due to heavy ion exposure. With the progressive scaling to smaller technologies, there is an increasing concern that circuits may be more susceptible to various mechanisms including Single Event Latch-up (SEL), Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR). In particular, the occurrence of SEL events happens when a parasitic NPNP feedback latch structure becomes biased into the on state due to a very dense track of electron–hole pairs which are created along the heavy ion track through the silicon [1]. This latch-up is self-maintained since there is a positive feedback path which sustains it and that requires an external power cycle in order to be deactivated [2].
The evaluation of permanent faults generation in modern Integrated Circuits (ICs) is of fundamental importance for several application fields. Environmental noises may generally provoke the generation of soft-errors, that temporarily affect the operational life of the electronic system but that can be corrected using the adequate countermeasures. Vice versa, permanent faults does not allow the electronic systems to be recovered, and if not preventively developed, the permanent fault affected electronic system may be definitively broken.
When safety critical applications, such as space, avionics or rail transport, are considered, statistics data indicates that a range between 10% and 40% of the whole faults may possibly turn into permanent fault generating a short on the power of the system [3]. It is therefore mandatory to adopt effective methodology to measure and subsequently protect electronic system versus permanent faults.
When a particle crosses a silicon junction, a coulombic interaction between the particle and the electrons is generated. This effect is common for all charged particles. When a charged particle traverses the silicon area, it loses energy through atoms ionization and excitation. The moving charged particle induce electromagnetic forces on atomic electrons and transfers energy to them. The energy transferred in a single electronic collision is only a small portion of the heavy charged particle energy, however through the whole traversing path, the energy can be considerably high. The energy is measured as linear rate of energy loss of a charged particle in a medium volume [4]. This quantity is extremely important in radiation physics, and it can generally be referred to with two names: stopping power or Linear Energy Transfer (LET). This quantity expresses the average energy transferred through traversing a given space of medium (−ΔE/Δx) [5].
In this paper we describe a new computer-aided design (CAD tool) that, in conjunction with silicon layout information and circuit behavioral functionality is able to depict the probability and the expected location where single event latch-up may happen and therefore to provide such kind of information to designers. From the scientific point of view, the main contribution of the present paper is to provide the complete method for the analysis and the evaluation of single event latch-up effects on integrated circuits implemented with radiation hardened technology. The main advantage of the proposed tool is the possibility to depict, once the design is in the early manufacturing stage, which is the expected SEL effect rate, and, possibly by using the feed-back provided by our tool, improve and reduce the SEL impact on the circuit. In particular, the proposed approach is able to provide an advancement in the scientific field of the measurement of the robustness of VLSI technology in safety–critical environment, since we provide the first tool able to predict the location and the probability of SEL effects giving the information related to the physical layout and to the electrical stimulus applied.
The proposed method has been validated through comparison with high temperature radiation test analysis of the SEL sensitiveness of MG2 Atmel radiation hardened technology [6]. The tests have been performed with heavy ion at the GANIL facility, Caen, France. Thanks to the radiation experiment, we compared the result provided by the developed sensitivity analyzer tool and we obtained a full compliance between them, thus demonstrating the effectiveness of the proposed method.
In this paper we present a novel tool for the estimation of the Single Event Latch-Up (SEL) effect on integrated circuits implemented with radiation hardened technology. We applied the developed techniques with the MG2RT Atmel radiation hardened technology. The experimental results we achieved demonstrated the efficiency of the proposed algorithm since the estimated cross-section is coherent with the ones obtained through radiation experimental analysis. Currently, according to the whole systems were the DUT will be used, we are evaluating the impact of the SEL and SEU effects on the whole application. Furthermore, our approach is able to identify the source of the SEL effects and to evaluate the impact of a dynamic workload applied to the DUT under high temperature and heavy ion irradiation.
