مدل سیستم C در سطح تراکنش چرخه دقیق برای یک باس ارتباط سریالی

This paper presents a transaction level SystemC model of an avionics mission system data bus that provides cycle-accurate simulation of the bus. The mission system is a complex distributed computer network consisting of a mission control computer, radars, an array of subsystems and sensors. The data bus plays a critical role in the system as it carries all the information between the system components. Therefore modelling the bus at an appropriate level of abstraction using appropriate technology is important for evaluation of the performance of both the bus and the entire system. While models based on traditional hardware description languages (HDL) provide cycle-accurate performance estimates they are very slow and have high code complexity. In order to enhance model performance this paper presents a transaction level model (TLM) utilizing the enhanced SystemC features and levels of abstraction. The TLM model incorporates a clock-based synchronisation strategy thereby providing cycle-accurate performance estimates like the HDL models. The developed model has been validated for various payloads and system sizes. Simulation results show that the proposed SystemC transaction level model is much more efficient than models developed using conventional hardware description languages.

SystemC is a high level Hardware Description Language (HDL) that comprises of C++ class libraries and a simulation kernel [1]. SystemC inherits the features of the C++ programming language. The Object-Oriented features of the C++ language helps in modelling a complex system in an easier way and allows the designer to analyse the performance of the model [2]. Also the concept of design reuse in SystemC reduces the modelling time compared to that of traditional hardware languages like VHDL [3] and Verilog [4]. It was reported in [1] that a SystemC model was able to achieve a speed ten times faster than a VHDL model at the same level of abstraction. SystemC is also considered to be more powerful for design validation when compared to VHDL and Verilog [5]. The ability of this language to incorporate different levels of abstraction within the same model provides flexibility in separating the functional specification of a system from the communication specification [6]. For the same system implemented in VHDL, the level of abstraction within a model is restricted to the structural domain [7]. In SystemC abstraction is supported by the C++ features like polymorphism, inheritance, template, class and objects. In VHDL the lack of separation between communication and functional specification makes the system design more complex while the reuse of designs is restricted to component level [1]. This paper presents a transaction level model (TLM) of a serial data bus in SystemC incorporating a clock-based synchronisation strategy to ensure cycle-accurate performance estimates. The model conforms to the military standard MIL-STD-1553. The data bus is the main communication component in an Avionics Mission System (AMS). An AMS is considered to be a real-time embedded system which includes standard and custom software and hardware [8]. In this paper we first briefly describe the communication protocol and the associated standard in Section 2. The modelling approach and some important features of SystemC supporting this approach are discussed in Section 3. The transaction level SystemC model of the serial data bus and the state diagrams are presented in Sections 4 and 5 respectively. Section 6 presents the testbench developed for simulation of the model and the specific SystemC features used for measurement of bus performance. Section 7 presents the simulation results and Section 8 concludes the paper.

A transaction level model of the Avionics serial data bus implemented using SystemC has been presented. The proposed model has been validated for various system size and payloads. The TL model has been found to be much more efficient than a behavioural VHDL model of the bus in terms of code size, code complexity, modelling effort and simulation time. A number of factors have contributed towards the efficiency of the model, namely the TLM approach allowing higher levels of abstraction, the separation of communication from computation and hiding the details of communication and computation. We have achieved a cycle-accurate executable model of the serial bus without the complexity inherent in register-transfer level models and behavioural models implemented using conventional hardware description languages. The model is able to determine message transaction times to the accuracy of a clock cycle, which ordinary transaction level models such as untimed or approximate-timed models [11] are not capable of doing. We have shown how to utilise the enhanced SystemC features and classes to implement the cycle-accurate TLM methodology for creating an efficient model of a serial communication bus. Since SystemC provides a common C++ based design environment for both hardware and software the TLM methodology presented in this paper will ease the hardware-software co-design of embedded systems with a sufficiently high level of abstraction while providing cycle-accurate performance evaluation. Designers of System-On-Chips (SoC) and distributed systems involving shared communication infrastructure (bus) will benefit from the clock-based high performance transaction level modelling approach presented in this paper.