یک الگوریتم زمان بندی آزمون جدید بر اساس شبکه های بر روی تراشه به عنوان مکانیزم دسترسی متن

Networks-on-Chip (NoCs) can be used for test data transportation during manufacturing tests. On one hand, NoC can avoid dedicated Test Access Mechanisms (TAMs), reducing long global wires, and potentially simplifying the layout. On the other hand, (a) it is not known how much wiring is saved by reusing NoCs as TAMs, (b) the impact of reuse-based approaches on test time is not clear, and (c) a computer aided test tool must be able to support different types of NoC designs. This paper presents a test environment where the designer can quickly evaluate wiring and test time for different test architectures. Moreover, this paper presents a new test scheduling algorithm for NoC TAMs which does not require any NoC timing detail and it can easily model NoCs of different topologies. The experimental results evaluate the proposed algorithm for NoC TAMs with an exiting algorithm for dedicated TAMs. The results demonstrate that, on average, 24% (up to 58%) of the total global wires can be eliminated if dedicated TAMs are not used. Considering the reduced amount of dedicated test resources with NoC TAM, the test time of NoC TAM is only, on average, 3.88% longer compared to dedicated TAMs.