مطالعه پیاده سازی سخت افزاری از چندین الگوریتم زمان بندی لینک خروج جدید

The provision of Quality of Service (QoS) in interconnection networks is required for new multimedia and time-sensitive applications, which are very important for recent utility computing data centers (UCDCs) using high performance networks. These interconnection networks support switch-based principles and establish high demands in terms of bandwidth, time-delay, and delivery over short distances. A key component for networks with QoS support is the egress link scheduling algorithm. Apart from providing a good performance in terms of, for example, good end-to-end delay (also called latency) and fair bandwidth allocation, an ideal scheduling algorithm implemented in a high-performance network with QoS support should satisfy another important property which is to have a low computational and implementation complexity. In this paper, we propose specific implementations (taking into account the characteristics of current high performance networks) of several fair-queuing scheduling algorithms and compare their complexity in terms of silicon area and computation delay. In order to carry out this comparison, we have devised our own hardware comparison methodology. Following this methodology, we have performed our own hardware implementation for the different schedulers. We have modeled the schedulers using the Handel-C language and employed the DK design suite tool from Celoxica in order to obtain hardware estimates on silicon area and arbitration time.