تخم ریزی کارآمد برای حافظه مشترک و پیام در معماری های چند هسته ای

We proposed an approach based on hardware-assisted task spawning on many-core systems [1]. In the current article, we present an extended version of our work for hardware-managed task spawning, keeping in view the communication requirements of both shared memory and message passing programming models. The proposed hardware support, integrated into the network interface architecture, reduces the synchronization overhead for task spawning. The software is offloaded from task spawning which results in an increase in the overall performance. The simulation results highlight that the proposed task spawning approach improves the overall performance up to 40% in comparison to an existing state-of-the-art approach [2]. To underline the applicability, we implemented an FPGA prototype to investigate real world applications. The investigations show that the proposed concept offers a low overhead in terms of implementation area cost on FPGA and ASIC platforms.