ترانسفورماتور: معماری ناهمگن قابل برنامه ریزی زمان اجرا برای شتاب کارهای پویا

Heterogeneous architectures face challenges regarding transparent acceleration as well as the allocation of resources to cores and accelerators. The “Transformer”, a run-time reprogrammable, heterogeneous architecture consisting of cores and reconfigurable logic with support for coarse-grained acceleration of the dynamic, unpredictable workloads present in mobile and cloud computing environments, is proposed as a solution. The architecture allows for the run-time instantiation of one or more acceleration functions, present in an on-chip reconfigurable logic, which responds to the demands of compute-intensive software libraries. The hardware controller and software wrapper functions are designed to profile workloads, reprogram the internal logic, and invoke the appropriate acceleration functions. Novel heuristics are derived with respect to the accelerator function scheduling. In order to optimize performance and power efficiency, the appropriate system parameters are explored, including the L1 and L2 cache sizes, the accelerator local buffer sizes, as well as the allocation of resources to the cores and accelerators. The simulation results indicate that the Transformer   provides significant improvements in terms of performance, up to 14×× for single-type workloads and 2.3×× for dynamic workloads, as well as energy efficiency, up to 6.9×× for various workloads.