معماری ADC بر مبنای قاعده کالیپر

In this paper, a new kind of architectures for the full-flash or subranging Analogue to Digital Converters (ADC’s) is presented. To describe these architectures and explain the intrinsic conversion procedure, we refer to a technique, already presented by the author, which improves the accuracy of a measurement system. This technique is based on the arithmetic of the integer numbers in finite fields and include, as a particular case, the well known “caliper rule”. The said technique is recalled and explained by using some simple measurement examples, in particular length, time and mass measurements. Then the technique is applied to the full-flash and subranging ADC architectures, greatly reducing the number of the resistors necessary to generate the voltage reference scale. Indeed, the required resistors for a n-bits conversion word length are reduced from 2n to about 3∗2n/23∗2n/2. This reduction and the particular comparison method involved in the theory allow the realization of full-flash architectures having large word lengths.