بهینه سازی ترانزیستور برای یک فناوری CMOS میکرومتر 0.13 با هزینه پایین و با کارایی بالا

This paper discusses the optimisation of a high performance, low cost 0.13 μm CMOS technology with a view on its further scaling to the 100 nm technology node. The focus is mainly on gate oxide (thickness and nitridation method), deep junction implants and annealing. It is shown that in order to take the full benefit of gate oxide thinning, low energy boron implants and spike rapid thermal anneal are mandatory for pMOS devices. The same route gives also promising results for nMOS transistors when gate predoping is used to reduce gate depletion.