تجزیه و تحلیل حساسیت آسیب ساختار پد باند کارآمد پیشرفته مس/k کم با استفاده از معیار انرژی آزاد منطقه

For integrated circuit (IC) wafer back-end development, state-of-the-art CMOS-technologies have to be developed and robust bond pad structures have to be designed in order to guarantee both functionality and reliability during waferfab processes, packaging, qualification tests, and, of course, usage. It is now well established that for future CMOS-technologies (CMOS065 and beyond), low-k dielectric materials will be integrated in the back-end structures. However, bad thermal and mechanical integrity as well as weak interfacial adhesion result in major thermo-mechanical reliability issues. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily induce cracking, delamination and chipping of the IC back-end structure when no appropriate precautions are taken. This paper presents an efficient method to describe the damage sensitivity of three-dimensional multi-layered structures. The index that characterizes this failure sensitivity is an energy measure called the Area Release Energy, which predicts the amount of energy that is released upon crack initiation at an arbitrary position along an interface. The benefits of the method are: (1) the criterion can be used as damage sensitivity indicator for complex three-dimensional structures; (2) the criterion is energy-based, thus more accurate than stress-based criteria; (3) unlike recent fracture mechanics approaches, no initial defect size and location has to be assumed a priori. A mesh objectivity condition is formulated resulting from numerical experiments. The method is applied to advanced IC back-end structures, revealing not only the most critical back-end design but also the critical interfaces in the bond pad structures at which delamination might occur. In order to bridge the length scale difference between the wafer level and the back-end structures, a multi-scale method has been implemented in the finite element code MSC.Marc. In this way, effects of e.g., packaging and wire bond loading at the global level can be studied while taking into account the possibility of occurring failure phenomena at the local, back-end level. The validity and applicability of the method will be demonstrated by considering several Cu/low-k back-end structures. The obtained results are in good agreement with experimental observations.

Due to the reduced design margins and shorter time-to-market in IC back-end process development, trail-and-error approaches are not sufficient anymore and a more sophisticated methodology based on numerical simulation and optimization techniques is required. With this virtual prototyping and qualification methodology thermo-mechanical reliability issues are already included in the design phase rendering proposed design changes more efficient and thus cheaper. It is now well established that for future CMOS-technologies (CMOS065 and beyond), low-k dielectric materials will be integrated in the back-end structures [1]. The thermo-mechanical reliability of bond pads due to the bad thermal and mechanical integrity of the low-k materials and associated interfaces, is still an important issue in the development of new Cu/low-k CMOS-technologies [2]. The resulting forces due to the wire bonding process, qualification tests and packaging processes can easily result in reliability problems like bond pad delamination and low-k cracking. However, bad thermal and mechanical integrity as well as weak interfacial adhesion result in major thermo-mechanical reliability issues. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily induce cracking, delamination and chipping of the IC back-end structure when no appropriate precautions are taken [3]. An important qualification test for wire integrity is the wire pull test. The typical configuration of this wire pull qualification test, where the wire is pulled by a hook, is visualized in Fig. 1a. The wire and the bond pad structures should withstand a certain force level before failure of the wire or the bonds occurs. Actually, two failure modes are possible: metal peel off and neck break, as illustrated in Fig. 1b. While the neck break failure mode is acceptable, the metal peel off mode (prior to neck break) is unacceptable as the occurring delamination in the back-end structures indicates that the integrity of the bond pad designs is not sufficient. An example of actual bond pad delamination of a CMOS90 Cu/low-k process due to this wire pull qualification is given in Fig. 2. Full-size image (28 K) Fig. 1. Schematic of the wire pull test. Figure options Full-size image (31 K) Fig. 2. Examples of bond pad delamination due to wire pull testing. Figure options The thermo-mechanical reliability of the (low-k) bond pads depends strongly on the underlying metal and via layout of the back-end layers. The copper metal lines and vias act as mechanical support in the relatively weak low-k matrix. Due to the complex interaction of multiple processes, materials and interfaces, however, an optimum metal layout design is difficult to lay out on beforehand. In order to rank the structural integrity of different bond pad designs, finite element analyses will be used allowing optimization of the bond pad structure in the design phase. The developed methodology is based on a three-dimensional multi-scale sub-modeling approach similar to Wang et al. [4]. However, in our paper, a dedicated homogenization procedure has been developed resulting in equivalent, fully anisotropic stiffness properties representing the mechanical behavior of the back-end structures at the global, packaging level. As a result, the displacements at the global level are calculated more accurately, compared with the approach proposed in [4]. Next, the so-called localization step permits to determine local field variables by using the global displacement solution field [5]. At both levels, the Area Release Energy (ARE), described in [6], will be calculated as failure criterion. More specifically, the amount of energy is calculated that is released upon delamination of an area of predefined size for any position along any interface without the need of an initial crack. The ARE value indicates the risk of delamination of the interfaces without knowing a priori the exact location of possible failure(s). This method will be used to study the damage sensitivity of several three-dimensional bond pad structures. The obtained results will be validated with experimental observations.

In this paper, an efficient way to determine the damage sensitivity of three-dimensional bond pad structures has been established. For this purpose, a 3D multi-scale method incorporating an energy-based failure indicator, the ARE criterion, has been presented for analyzing delamination in Cu/low-k bond pads. A mesh objectivity condition for the ARE values is formulated which results from numerical experiments. Although the crack area is assumed circular (penny-shaped crack), being more realistic than a square one, the influence of the crack geometry will be studied in future work. The multi-scale methodology, consisting of a homogenization and localization step combined with periodic boundary conditions, provides a way to perform numerical simulations at the global level while taking into account the details of the local level. The Area Release Energy method showed that the failure sensitivity of different three-dimensional structures could be evaluated efficiently by means of the resulting contour maps: a qualitative comparison of the integrity of the local bond pad structures resulting from the imposed boundary conditions at the global packaging level is thus feasible. No initial cracks or imperfections had to be inserted in the models. The method thus allows a ranking between the different three-dimensional bond pad designs. The global results confirmed the experimentally observed critical interface location and the most failure sensitive local structure. It is not known if and how the results change if residual stresses and the wire bonding process will be taken into account in the models. The results of the local models confirmed the least favorable structure while also details of the different interface loading conditions are obtained which facilitates taking into account the difference in interface strengths of the different interfaces. The influence of the length scale has been shown. This value should either be related to geometrical details of the back-end structures and/or to the non-uniformity of the state variables in the structures. Nonetheless, experimental results are necessary to validate these possibilities.