تجزیه و تحلیل عملکرد از پروتکل BusNet برای ارتباطات بین پردازنده مبتنی بر اتوبوس روتر

Nowadays, backplane bus-based multiprocessor systems often utilize the standard network protocol such as TCP/IP for communication between processors on the backplane bus. In such systems, it is common for the backplane bus to emulate the standard MAC protocols such as CSMA/CD. This paper aims to analyze the delay performance of the MAC emulation-based backplane network by constructing queueing models based on detailed bus operations. For this purpose, we choose BusNet as a target protocol. BusNet is an ANSI standard network protocol and its specification contains basic operations commonly used in most backplane buses. We investigate the throughput-delay characteristics in terms of packet size, block transfer scale, and arbitration scheme. We also compare the packet delay in BusNet with the IEEE 802.3 CSMA/CD network which BusNet is expected to be compatible with. The simulation result shows how an optimal block transfer scale can be determined in respect of the performance trade-off between BusNet and other real-time traffics.

Backplane buses are widely used for interconnection between processors, memory subsystems, and I/O devices in multiprocessor systems. Multiprocessor systems interconnected over a backplane bus provide cost-effective solutions for a range of parallel and distributed computing applications. Processors in such systems typically communicate with each other by accessing directly the distributed and/or unified shared memory through the backplane bus protocol. Recently, with rapid advances in computing and communication technologies, the application software is commonly involved in complicated interprocessor communication. As a result, the modern trend is to use standard network protocols such as TCP/IP on the backplane bus. This gives advantages such as portability, robustness, and rapid prototyping at the expense of slight performance degradation. These backplane network protocols commonly emulate the standard medium access control (MAC) protocols such as CSMA/CD in order to interface the existing upper protocol stack, i.e. IP. This approach gives an additional advantage in costs because application software can utilize standard network protocols without equipping every processor board with a network interface card (NIC). Despite the growth of usage and the benefit of backplane network protocols, however, there has been little work regarding the performance of the backplane bus as a communication medium. Eventhough the bandwidth of the backplane bus is generally larger than that of the local area network, detailed performance analysis is essential in order to guarantee both timely and logically correct behavior. In this paper, we develop and validate an analytic model to study the MAC and link layer characteristics of the backplane network. Numerous works have been carried out concerning the performance of the MAC protocols, but have mostly focused on the conventional local area networks such as the token passing and CSMA/CD networks. In particular, CSMA/CD has been extensively analyzed for the past two decades [1], [9], [11], [14], [15] and [18]. Compared with the local-area networks, however, the backplane bus exhibits quite a different behavior in delay performance due to the physical channel characteristics. Several works deal with the physical features of the backplane buses. Bain and Ahuja perform a simulation study on a static priority arbiter, a rotating daisy chain, and an ideal FCFS arbiter [2]. Assuming fixed bus access time and uniformly distributed inter-request time, they measure the mean and the coefficient of variation of the waiting time for the data transfer request. Vernon and Leutenegger analyze the bus arbiters using a timed Petri-net model [19]. Their performance metric is the mean processor efficiency, i.e. the bus bandwidth allocated to each processor. They also discuss the fairness of the arbiters. Woodbury and Shin construct a queueing network model to study a workload effect on performance for a unibus multiprocessor [20]. Assuming prioritized arbitration, they present the waiting time for each priority class traffic. Recently, several works have been presented which investigate the commercial backplane buses in detail. Johnson et al. model the arbitration phase of the Futurebus+ as an M/G/1 queue and estimate the performance achievable by the virtual port memory multiprocessor system [7]. Kettler and Strosnider give a formal model for the MCA bus by analyzing the components comprising the data transfers [8]. A similar approach for the Controller Area Network (CAN) bus is taken by Tindell et al. [17]. However, most of these researches do not give a suitable model for the packet-based communication over the backplane bus. They lack in consideration for the packet-oriented data transfer or concentrate on estimating bus bandwidth allocated to each processor. For the communication performance, their analytic models are inadequate or need further investigations. In this paper, we aim to analyze the packet transfer delay in the backplane bus network by taking into account the physical bus channel characteristics. Assuming each communicating node is associated with a queue of infinite capacity, we devise queueing systems where a packet request is served by a group of basic bus transfers called transactions. Unlike traditional packet service models where the entire packet transmission is non-preemptive by nature, packet transmission on the backplane bus can be preempted by other ready nodes since the bus is shared on the transaction basis. The accuracy of the analytic model is validated by a simulation study using a bus simulator which is constructed to reflect bus details. Using the analytic model, we discuss the throughput-delay performance of the backplane network in comparison with that of the conventional CSMA/CD network. We also present extensive experimental results obtained for various values of packet size, block transfer scale, etc. For generality, we choose BusNet [22], [23] and [24] as a target protocol. BusNet is an MAC and link-layer protocol specification for the standardized communication over the VMEbus. Since its specification contains only primitive features commonly used in most backplane hardware, the analysis can be extended to different kinds of backplane buses without any difficulty. The rest of this paper is organized as follows. In Section 2, we introduce the concept of backplane bus network protocol. We also briefly describe the arbitration schemes and data transfer mechanism in VMEbus. In Section 3, we analyze the packet transfer time in BusNet. Section 4 presents numerical results of the analytic model and discusses the communication performance. This paper ends with concluding remarks in Section 5.

Backplane bus network protocols are widely used for interprocessor communication in a multiprocessor system. In this paper, we have studied the performance of the backplane network protocol considering the MAC characteristics. We analyzed the mean packet transfer delays under two arbitration schemes, i.e. PRI and FAIR. For an accurate analysis, we developed a detailed bus transaction model which investigates the physical bus features in detail such as the block transfer and overlapped arbitration. In the PRI mode, BusNet shows a significant variance of delay among participants. In particular, the participant with the highest priority is most favored so that the delay increase is kept well under 13% throughout the bus throughput. BusNet is relatively insensitive to the packet size. In the FAIR mode, packet size has little effect on the delay performance. For the PRI mode, the average delay is unaffected by the packet size although the delay variance is minimized among participants when the packet is small enough to be contained in a transaction. This contrasts with the CSMA/CD network where short packets significantly degrade the delay performance. We also examined the effect of bus parameters such as the block transfer scale and overlapped arbitration. Without block transfer, the achievable bus throughput is at best 0.75. By utilizing the block transfer, we can obtain the bus throughput almost close to one. Furthermore, the transfer delay is significantly reduced. Although the block transfer mechanism greatly improves the delay performance, however, we observed that an optimal block transfer scale should be determined considering the undesirable effect of block transfer on the real-time performance. Although our analytic model has been developed based on the VMEbus, it assumes only basic features commonly used in most backplane hardware and can be easily applied to other bus network protocols with different kinds of backplane buses.