Low-voltage high-gain large-capacitive-load amplifiers in 90-nm CMOS technology
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A new 0.35 μm CMOS electronic interface for wide range floating capacitive and grounded/floating resistive sensor applications
LECTOR: A Technique for Leakage Reduction in CMOS Circuits
Low Thermal Budget Monolithic Integration of Evanescent-Coupled Ge-on-SOI Photodetector on Si CMOS Platform
New Subthreshold Concepts in 65nm CMOS Technology
A CMOS Inverter-Based Class-AB Pseudo Differential Amplifier for HF Applications
1-Bit Sub Threshold Full Adders in 65nm CMOS Technology
Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology ☆
HKMG CMOS technology qualification: The PBTI reliability challenge
Modification of standard CMOS technology for cell-based biosensors
POSFET Tactile Sensing Arrays using CMOS Technology ☆
Visible and NIR integrated Phototransistors in CMOS technology
A new write assist technique for SRAM design in 65 nm CMOS technology
New configuration memory cells for FPGA in nano-scaled CMOS technology
A new asymmetric 6T SRAM cell with a write assist technique in 65 nm CMOS technology
Ultrathin DPN STI SiON liner for 40 nm low-power CMOS technology
High-speed photodiodes in 40 nm standard CMOS technology
New carbon-based thermal stability improvement technique for NiPtSi used in CMOS technology
Ultra-low Offset Vertical Hall Sensor in CMOS Technology ☆
Challenges of nickel silicidation in CMOS technologies ☆
Facet engineering for SiGe/Si stressors in advanced CMOS technology
Prospect of the future of switched-current circuits with regard to future CMOS technologies
Design of an L1 band low noise single-chip GPS receiver in 0.18 μ m CMOS technology
Review of fuse and antifuse solutions for advanced standard CMOS technologies ☆
High linearity, low power RF mixer design in 65 nm CMOS technology
Characterization of symmetrical spiral inductor in 0.35 μm CMOS technology for RF application
Passive mixer with OPA filter for DVB-H front-end in 65 nm digital CMOS technology
Analysis on the mutual inductance of planar transformer in CMOS technology
Electrical characterization of thulium silicate interfacial layers for integration in high-k/metal gate CMOS technology
Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies ☆
High mobility CMOS technologies using III–V/Ge channels on Si platform
Integration of NEMS resonators in a 65 nm CMOS technology
POSFET tactile sensing arrays using CMOS technology
SrHfO3 as gate dielectric for future CMOS technology
Optimum bias of power transistor in 0.18 μm CMOS technology for Bluetooth application
The development of scalable sensor arrays using standard CMOS technology
Investigation of triple-junction photodetector in 90 nm CMOS technology
High-speed wavefront sensor compatible with standard CMOS technology
Crosstalk effects in mixed-signal ICs in deep submicron digital CMOS technology
A novel topology for grounded-to-floating resistor conversion in CMOS technology
Growth of lanthanum oxide films for application as a gate dielectric in CMOS technology
Sector split-drain magnetic field-effect transistor based on standard CMOS technology
The Ge condensation technique: A solution for planar SOI/GeOI co-integration for advanced CMOS technologies?
Full-chip leakage analysis for 65 nm CMOS technology and beyond
Towards implementation of a nickel silicide process for CMOS technologies
Investigation of iridium as a gate electrode for deep sub-micron CMOS technology
Silicon nanowire sensor array using top–down CMOS technology
Quasi-planar bulk CMOS technology for improved SRAM scalability
Design and implementation of a capacitive fingerprint sensor circuit in CMOS technology
The temperature characteristics of bipolar transistors fabricated in CMOS technology
First Vertical Hall Device in standard 0.35 μm CMOS technology
Temperature cross-sensitivity of Hall plate in submicron CMOS technology
A spice-like reliability model for deep-submicron CMOS technology
A fully integrated dual-band VCO by 0.18 μm CMOS technologies
Ultra-high temperature (>300 °C) suspended thermodiode in SOI CMOS technology
Transistor optimisation for a low cost, high performance 0.13 μm CMOS technology
Ultra-thin silicon nitride by hot wire chemical vapor deposition (HWCVD) for deep sub-micron CMOS technologies
An improved design and simulation of low-power and area efficient parallel binary comparator
An accurate 1-V threshold voltage reference for ultra-low power applications
High speed and low cost synchronous counter design in quantum-dot cellular automata
Current conveyor-based differential capacitance analog interface for displacement sensing application
Study of capacitance nonlinearity in nano-scale multi-stage MOSFET-only sigma-delta modulators
A Content-Addressable Memory structure using quantum cells in nanotechnology with energy dissipation analysis
Design of ultra low power current mode logic gates using magnetic cells
Efficient parasitic-aware hybrid sizing methodology for analog and RF integrated circuits
A new approach to frequency-domain noise analysis and design of a very-low noise amplifier in radio and microwave frequencies