چارچوب شبیه سازی اجزای جانبی بین اتصال اتوبوس و نتایج شبیه سازی در محدودیت بین زمان تاخیر اجزای جانبی استاندارد 2.1

We describe a simulation environment that allows us to simulate the standard peripheral component interconnect (PCI) bus protocol, as well as modified PCI protocols. While there are standard benchmarks (such as the SPEC [IEEE Comput. 33 (7) (2000) 28] benchmarks) available for processor simulation, database system simulation, and now even for simulating embedded systems (from EDN Embedded Microprocessor Benchmarking Consortium, EEMBC, http://www.eembc.org), there are no standard benchmarks for simulating computer buses in general and specifically, for simulating the PCI bus. To address this problem we describe a methodology for gathering information about the PCI traffic from a real system, and to use this information in order to generate PCI cycles that drive the simulator for both standard and modified PCI protocols. Finally, we use the simulation environment to run experiments with various parameters of the standard PCI protocols, and an extension that involves transferring a hint about the expected latency on the data bus at the time the target ends the current burst transaction.

In addition to the CPU, PC systems include other essential components that are often neglected in computer architecture research and textbooks; two notable exceptions are [1] and [2]. One of these essential components is a bus or multiple buses, which connect the various subsystems of a computer system [3]. Since its first release by the peripheral component interconnect (PCI) Special Interest Group, an organization formed in 1992 to develop the PCI local bus Specification, the PCI bus [4], [5], [6], [7], [8], [9] and [10] has become an industry standard, implemented in almost all PC systems as well as in some workstations [11] and servers [12]. More recently, PCI buses have been also reconfigured for industrial applications and embedded systems [13]. The PCI bus performance has a critical impact on the overall system performance in many applications [14], [15], [16], [17], [18] and [19]. The advantages of simulation are well known [20], and there are many simulation environments available to the computer architecture research community for various computer systems and subsystems. Yet, despite the predominance of PCI, to our best knowledge no simulation environment was available in the public domain for simulating the PCI bus system before the work presented in this paper. The first part of this work describes the implementation of a simulation framework that allows us to simulate the standard PCI bus protocol, as well as modified PCI bus protocols. Next we describe a methodology for gathering information about the PCI traffic from a real system, and to use this information in order to generate PCI cycles that drive the simulator for both standard and modified PCI protocols. Finally, using the simulation environment and the data gathered about the PCI traffic as an input to it, we provide some results on PCI bus latency limitations and consider a modified PCI protocol that addresses the latency problem.

We have designed and implemented a performance analysis and simulation framework that allows us to gather statistical information about the PCI traffic from a real system, generate PCI traffic using the standard PCI protocols as well as modified PCI protocols, and simulate PCI bus protocols and extensions. We have run simulations of a single master device, using the standard PCI protocol, as a function of the initial retry threshold and master retry overhead. Still using the standard PCI protocol, we have simulated multiple bus masters, with different combinations of two parameters, the MLT and the MTT. We have determined a set of parameters that produced minimum run time in simulations of the standard PCI protocol. Using these parameters, we have then simulated a modified PCI protocol including a target retry hint extension, and compared the results with results achieved with the standard PCI protocol. For the same simulation setup we have found a performance increase of up to 4.5% over the standard protocol; the improvement is not higher than that for the following reasons: 1. When a target disconnects without delivering data, a master must give up the bus, letting other masters do some work. In most cases this means that when the bus bandwidth is needed, the master that must re-issue the request would not get the bus too quickly anyhow, so by the time it actually gets the bus back, the target is ready. 2. The MTT makes sure that the other master is guaranteed a minimum time slice even when it has short transactions, so this guarantees a minimum time before the original master would get a chance to retry the cycle. The latency hint extension is a simple modification of the PCI standard 2.1 that provides modest performance improvement. Substantially higher improvement would involve split transactions and out of order data transfers. As for future work, other extensions of the PCI standard may be investigated. For example, another extension, which also solves the latency problem, consists of adding a new read command that allows queuing a read command, specifying not only the base address but also the length and an ID tag. The ID tag is used by the target to identify the resulting data when it is ready. The master sending the request will tag the reply by an ID code. The device number, bus number and function number of the requesting device could be used as an ID tag. The effect of this extension on the PCI bus, however, is more complex in terms of transaction ordering. The PCI standard specifies very specific transaction ordering rules, and we must inspect their implications on the split transaction enhancements.