فعال کردن مدل سازی دقیق از قدرت و مصرف انرژی در سیستم مبتنی بر ARM بر روی تراشه

Motivated by the importance of energy consumption in mobile electronics this work describes a methodology developed at ARM for power modeling and energy estimation in complex System-on-Chips (SoCs). The approach is based on developing statistical power models for the system components using regression analysis and extends previous work that has mainly focused on microprocessor cores. The power models are derived from post-layout power-estimation data, after exploring the high-level activity space of each component. The models are then used to conduct an energy analysis based on realistic use cases including web browser benchmarks and multimedia algorithms running on a dual-core processor under Linux. The obtained results show the effects of different hardware configurations on power and energy for a given application and that system level energy consumption analysis can help the design team to make informed architectural trade-offs during the design process.

Energy efficiency is one of the primary design constraints for mobile devices that need to operate autonomously for as long as possible [1]. The current rate of battery life improvement of around 5% per year [2] means that the limited energy budget could delay the introduction of the future chips needed to support workloads whose complexity increases by one order of magnitude every 5 years [3]. Additionally, minimizing power consumption reduces the amount of heat dissipated requiring lower cost packaging, cooling solutions and increasing device reliability. Available studies show that a 10° increase in working temperature causes a 100% increase in failure rate [4]. The first action required to achieve the objective of minimizing energy or power consumption is to understand how the available energy budget is being used in the system [5]. This means that not only the main components such as the processor cores should be considered, but the whole system should be analyzed using real workloads as inputs to account for the dependency of power on the dynamic behavior of applications. These analysis results should be available before the device has been fabricated and should be accurate enough to guide the design team in the process of making architectural decisions leading to a solution superior in power and energy terms. Fig 1 depicts the typical main components that can be found in a modern mobile phone. This paper focuses on the interaction of the application processor and the memory subsystem. These parts account for roughly 30–50% of the total device power budget in compute intensive applications such as media playing [5]. The power consumption of the LCD/backlight combination and radios are the two other main component drains in the system but they are considered to be beyond the scope of this work. With these constrains in mind the present work contributions are as follows:

This research has presented a power modeling methodology based on power models developed using post-layout data and regression analysis. The usage of post-layout data enables a level of accuracy not possible with previous approaches that do not consider the implementation effects. The extension of the methodology to include the rest of the components in the system requires the addition of power models based on data sheet information or physical measurement for third-party components or components with no RTL description. The investigation is based on a realistic scenario in which a set of standard benchmarks are run after booting Linux in a multiprocessor hardware. The results highlight the importance of considering the whole system from a power point of view showing how changes in the system architecture can reduce CPU energy but increase system energy or increase average CPU power but reduce average system power. The experimentation shows that an energy reduction of 34% can be obtained replacing a 128 KB L2 cache with a similarly configured 1024 KB L2 cache during Firefox web browsing although the effects on CPU energy are much more modest. As future work we plan to investigate how the power models can be used in a high-level simulation environment to speed up power estimations. Additional refinements of the methodology will consider power control techniques such as dynamic voltage frequency scaling and also its extension to include static power. The power and energy results have been initially validated against applying the same methodology to an independent validation application set but an experimental board is also under development that will enable direct power measurements of the System-On-Chip and memory subsystem for further verification and correlation with the estimated results.