FPGA مبتنی بر ابزار آزمونگر برای سیستم های زمان واقعی ترکیبی

This paper presents a design methodology for a hybrid Hardware-in-the-Loop (HIL) tester tool, based on both discrete event system theory, given by timed automata, and continuous systems theory, given by difference equations. It is implemented using an FPGA platform that guarantees speed enhancement, time accuracy and extensibility with no performance loss. We have focused on the implementation of a discrete event system, specifically timed automata into FPGA, and we have linked them with continuous systems implemented as filters in fixed point arithmetic. The paper shows a methodology, which employs widely used tools (Matlab, UPPAAL) as a user interface, and which implements the FPGA based tester tool.

Hardware-in-the-Loop (HIL) applications are used by design and test engineers to evaluate and validate, e.g. vehicle components (electronic control units, etc.), during the development of new systems. Rather than testing these components in complete system setups, HIL allows the testing of new components and prototypes, so called Implementation Under Test (IUT). Replacing the rest of the system by a model implemented in a computer (Tester tool) increases the flexibility and the rate of test scenarios. The physical components being tested respond to the simulated signals as if they were operating in a real environment. Therefore, they can not distinguish between the signals sent by other physical components and signals provided by models running on a computer. This paper presents the design methodology of a tester tool. The objective of the tool is to check the behavior of the IUT while simulating the behavior of the controlled system. The tool has to be able to automatically analyze the behavior of the IUT and to vary the parameters of the system so that the IUT is forced to operate in different conditions. In most applications, the controlled system incorporates complex dynamics of physical nature, usually captured as a continuous change of continuous states on one hand and as complex dynamics of logic nature conveniently modeled by discrete states and events on other hand. Therefore, our tester tool is a hybrid, i.e. it is based on both the discrete event system theory, given by timed automata [3], and continuous systems theory, given by difference equations [23] and [24]. In order to avoid implementation errors, a high level of specification is required, so that the application expert can easily implement the system model, test cases and their analyses. The choice of such high level specifications, which are widely supported, enables us to execute a preliminary analysis (using Matlab/Simulink or UPPAAL) without incorporating any specific hardware, which simplifies the implementation of the tester tool. Fig. 1 shows a setup of the tester tool. The system model block emulates environment interacting with IUT. It is given by the timed automata and by the difference equations. The tester block includes test cases and checks the behavior of the IUT. It is collection of timed automata executing a test and monitoring specified properties.Simulation tools for continuous systems (like Matlab-Simulink) and model checking tools for discrete event systems (like UPPAAL) are often used during the analysis and design phases of hardware and software designs (e.g. [18] and [17]). Such model based designs usually lead to a modular structure, and the behavior of the modules is often analyzed separately in different tools, especially in the case of complex hybrid systems that are not tractable in polynomial time. On the other hand, the testing phase of the model based design requires a compact solution in order to describe the complete system behavior. Therefore, in this article, we have followed this practice: we have assumed separate modules of the system, which are described and analyzed by appropriate tools (widely treated in the literature [7] and [16]) and we have used these models as parts of the hybrid tester tool. Our tester tool is implemented by using the FPGA platform that guarantees, not only speed performance, but also time accuracy, and has quite good extensibility with no performance loss as well. Compared to the operating system based platforms, the FPGA platform is able to achieve a much faster sampling frequency. Moreover, the FPGA platform is not affected by the rather complex behavior of the operating system services, interrupt handling, etc. In contrast to the typical sampling period of 10 μs achieved in real-time operating systems like RTLinux [11] or OCERA [25], a sampling period of less than 100 ns can be achieved on the FPGA platform. More importantly, is the fact that, the FPGA platform has zero jitter since it is synchronous HW, and the separate parts do not influence each other. On the other hand, the operating system based platforms are well supported by widely used development tools.

The tester tool shown in this paper enables one to prove the quality of the developed controllers without them actually being assembled in the final product. Testing the considered class of applications requires a high sampling frequency, low jitter and scalability. Therefore, we have chosen an FPGA platform, synchronous logic hardware, capable of achieving a high degree of parallelism. Due to the hybrid nature of industrial applications, the presented methodology combines discrete event systems and continuous systems using timed automata and transfer function representation. The sampling period of the tester tool is given by the length of the FPGA clock cycle and by the number of the FPGA clock cycles needed to evaluate the continuous part and the discrete part. The shortest possible FPGA clock cycle is about 50 ns, assuming a continuous system of the third order and a 24-bit fixed point arithmetic unit on Xilinx Virtex 4. The existence of the urgent locations and channels in the timed automaton requires repetitive calls of the corresponding timed automaton function, which gives the number of the FPGA clock cycles needed to evaluate the state of the timed automaton. In normal applications (free of timed automata with long sequences of urgent locations), one can easily approach the sampling period in hundreds of ns. If, an even shorter sampling period is required, then it is necessary to change the quantization of the continuous values to a smaller set of discrete values, that can be handled by smaller arithmetic units leading to a shorter clock cycle. Moreover, using FPGA, used as the synchronous logics, jitter is less than one clock cycle. The scalability of our tester tool is given by the size of the FPGA only. Due to the physical parallelism, the blocks do not influence each other. On the other hand, when time and continuous variables require wide data buses, the number of FPGA interconnections increase and becomes a limiting factor (both for system model description and tested properties) of the presented method. In the future, we will focus on the interfaces, namely improvement of ADC and DAC. Further work will also deal with a dynamic reconfiguration of the FPGA that can be considered for on-line execution of test cases and automation of the testing process. Since we are using the same formalism in the discrete event system part, one may also consider to join the automatic test generation by UPPAAL-COVER and the test execution in our tool running at a very high time resolution. Currently, we are using a Linux OS running on the PowerPC hard core hosted on the same chip. This enables us to increase the flexibility and divide the problem into a HW (set of FPGA coprocessors) and SW part. We are also considering using Allen’s interval algebra [1] for the generation of the test properties. It proposes 13 basic relations between the time intervals and the operations on them. The basic relations are precedes, meets, overlaps, finished by, contains, starts, equals, started by, during, finished, overlapped by, met by and preceded by. Operations on relations are complement, composition, converse, intersection and union. The test generation approach based on this algebra has been presented in [10], where it is used for SysML temporal observer design