مطالعه شبیه سازی عایق فرمت سیلیکون کم عمق در هیچ چیز برای کاربردهای دمای بالا

This paper analyzes the effect of temperature variation on various device architectures i.e. Insulated Shallow Extension Silicon On Nothing (ISESON), ISE and SON MOSFET using ATLAS 3D device simulator for 45 nm gate length. The simulation results obtained with the ATLAS has been validated by comparing it with reported experimental data of SON MOSFET. The simulation results demonstrate that out of three device designs, the ISESON MOSFET is the most suitable device for high speed, low voltage and high temperature applications. The integration of ISE and SON onto the conventional bulk MOSFET leads to the enhancement in analog device performance in terms of device efficiency (gm/Ids), device gain (gm/gd), output resistance (Rout) and early voltage (Vea).

MOSFETs are widely used in amplifiers design, analog ICs, digital CMOS design, power electronics and switching devices for high temperature applications in the area of nuclear power plant and space applications, etc. Therefore, there is practical need for a temperature independent advanced MOSFET architecture that can also reduced the SCEs efficiently. Various impacts of high temperature operations are reduction in threshold voltage, off current (Ioff) and the drain current due to mobility degradation and increase in intrinsic carrier concentration [1]. At high temperatures lattice scattering dominates that leads to the reduction in carrier mobility. The silicon on insulator (SOI) architecture have been considered as a potential candidate for CMOS device due to the effective suppression of short channel effects (SCEs) and improved device performance [2]. But the SOI put the physical limits on the channel and buried oxide thickness [3] for sub-100 nm gate lengths. Furthermore, the coupling between the source and drain through the buried layer cannot be decreased when the silicon film thickness of SOI continuously reduces to suppress SCEs. Hence the insulating layer (SiO2) has been replaced with air having lower dielectric permittivity that can further reduce the junction- and parasitic-capacitance [4]. Due to the lower thermal conductivity of air as compared to SiO2, enhanced self heating effect is expected as the main potential drawback of SON. In order to further suppress the SCE, caused by the potential coupling between the source and drain through thin buried oxide (air) of SON MOSFET, an additional dielectric pillar [5] (i.e. Insulated Shallow Extension ISE) has been incorporated at the side walls, as shown in Fig. 1, of the channel except at the upper most part i.e. region at which the inversion layer is formed. Due to the presence of additional dielectric pillars at the vertical side walls, the punch-through current path is interrupted which leads to significant improvement in SCEs and reduction of the off current (Ioff) in ISESON architecture. The present work investigates the electrical performance (i.e. device gain (gm/gd), device efficiency (gm/Ids), output resistance (Rout), early voltage (Vea) and Ion/Ioff ratio) of ISESON MOSFET over a wide temperature range and compared the same with the novel ISE and SON MOSFET using ATLAS 3D device simulator [6]. All device architectures have been optimized for same threshold voltage i.e. Vth = 0.25 V @ Vds = 0.5 V by adjusting the metal gate work function.

A close comparison of various device architectures such as ISE, SON and ISESON for high temperature analog performance has been examined through extensive device simulations and the ISESON architecture shows the significant improvement against the temperature variation and analog performance. The ISESON MOSFET can overcome the critical problem of SCEs and further improve the immunity against the temperature in nano-scale regime due to the reduced coupling between source and drain region through buried oxide and the side pillars. Thus, ISESON is a good candidate for high temperature, low voltage and low power applications.