مطالعه شبیه سازی یک گیت منطقی مغناطیسی الکتریکی قابل خواندن و نوشتن

In order to keep up with economic growth and competitiveness the performance of microelectronic components will continuously increase, thanks to the introduction of new device types and materials. Spin based technologies are promising candidates because of their fast switching capability, high endurance, and non-volatility. Furthermore, the use of spin as a degree of freedom permits the combination of information storage and processing in a single device creating a fully non-volatile information processing system and thus allowing an even denser layout of simplified building blocks. Recently a fully electrical read–write 1 bit demonstrator memory device out of a ferromagnetic semiconductor has been shown and it has been proposed to extend this device to a logic XOR gate. However, up to now neither the feasibility of this gate nor the extendability to further logic gates has been shown. In this work we carried out a rigorous simulation study of the proposed logic gate. We are able to show that firstly the magnetization can be switched diagonally. Secondly, by changing the relative angle between the current flow path and the magnetization, not only a XOR gate is feasible but also (N)AND and (N)OR gates can be realized.

Diluted magnetic semiconductors (DMS) belong to the group of extensively studied (prototype) materials for future devices [1]. Especially one member of this group – (Ga,Mn)As – is of interest due to its compatibility with established semiconductor technology, carrier mediated ferromagnetism caused by sp–d exchange [2], and its cubic anisotropy which can be modified to an in-plane bi-axial anisotropy (View the MathML source) for compressively strained thin films or an easy axis out of plane (View the MathML source) for tensile strained thin films [3]. Hümpfner et al. [4] showed that by lithographical means local stress relaxation can be used to taylor the local anisotropy type. It was demonstrated that due to anisotropic stress relaxation, leads along View the MathML source and View the MathML source exhibit uni-axial anisotropies along these axes, respectively. Mark et al. [5] connected two pairs of such leads (along View the MathML source and View the MathML source) with a disk exhibiting a bi-axial anisotropy and thus enabled a realization of an electrically writable 1 bit demonstrator device. They also proposed an electrically read- and writable XOR gate consisting of two disks connected by a small constriction. Pappert et al. [6] connected two orthogonal and uni-axially relaxed leads by a small constriction and showed that the overall electrical resistance of the structure depends on the angle between the current flow View the MathML source and the local magnetization View the MathML source at the constriction. For a small constriction (∼tens of nanometers) and View the MathML source the structure exhibited a several times bigger resistance (up to more than 5 times) compared to View the MathML source. Therefore, combining two disks with bi-axial anisotropies, uni-axial leads, and a constriction connecting the disks, allows to combine memory and logic in one structure. Additionally this device allows an even denser layout on top of the density gain by scaling due to the merging of logic and memory units. We show that the disks can be switched by horizontal and diagonal current flow, scaling leads to smaller switching times, and the possibility of further logic gates by changing the angle between the current density View the MathML source and the magnetization View the MathML source at the constriction.

It was found that the device can be switched by a horizontal current flow path as well as a diagonal current passing through the constriction. However, due to the differences in starting and ending energies as well as the pinning of the magnetization at the constriction, a horizontal flow path is more reliable (≈30% to ≈90% and a total average of 75.5% for x-flow View the MathML source and a total average of 97.5% for x-flow d2; and View the MathML source and a total average of 41.8% for diagonal flow) and faster (x-flow View the MathML source to View the MathML source; x-flow View the MathML source to View the MathML source; d-flow: View the MathML source to View the MathML source). Furthermore, one can engineer different kinds of logic gates by changing the relative position of the disks, rotating the layout or the crystal orientation, and/or utilizing different magnetization orientations for operation. Since by this approach (N)AND, (N)OR, and XOR gates are available, basic building blocks for arbitrary complex logic functions are at hand and open the possibility of non-volatile information processing.