منابع ترکیبی از نوسانات پارامتر ذاتی در نانومتر نسل UTB-SOI MOSFET : یک مطالعه شبیه سازی آماری

The ultra thin body (UTB) SOI architecture offers a promising option to extend MOSFET scaling. However, intrinsic parameter fluctuations still remain one of the major challenges for the ultimate scaling and integration of UTB-SOI MOSFETs. In this paper, using 3D statistical numerical simulations, we investigate the impact of random discrete dopants, body thickness variations and line edge roughness on the magnitude of intrinsic parameter fluctuations in UTB-SOI MOSFETs. The sources of intrinsic parameter fluctuations, which can be separated in simulation, will occur simultaneously within a single MOSFET. To understand the impact of these sources of fluctuation in an actual device, simulations with all sources of intrinsic parameter fluctuations acting in combination have also been performed.

With the progressive scaling of conventional MOSFETs to nanometre dimensions, variations in transistor characteristics due to random discrete dopants, interface roughness and line edge roughness start to adversely affect the yield and functionality of circuits constructed from them [1] and [2]. Due to the scaling limitations of the conventional MOSFETs, novel device architectures, such as UTB-SOI and multi-gate MOSFETs, that are also more resistant to some of the sources of intrinsic parameter fluctuations, are anticipated to play an increasingly important role before the end of the current ITRS [3] roadmap. UTB-SOI transistors with virtually undoped channels have superior electrostatic integrity and better performance compared with bulk MOSFETs. Working UTB-SOI MOSFETs with a channel length of 6 nm [4] and body thickness down to 3 nm [5] have already been successfully demonstrated. The optimal scaling of the UTB-SOI MOSFETs to such dimensions, however, requires a body thickness in the range of nanometres. At such dimensions, local variations in body thickness, geometry variations, due to line edge roughness and discrete random doping in the source–drain regions, will have a dramatic impact on their characteristic. While UTB devices offer a potential solution to ultimate MOSFET scaling, obtaining reliable initial estimates for the magnitude of their corresponding intrinsic parameter fluctuations becomes extremely important. This work presents a systematic analysis of the intrinsic parameter fluctuations (IPF) in ultimate UTB-SOI MOSFETs using 3D Drift Diffusion ‘atomistic’ simulations [6]. The UTB-SOI MOSFETs are designed to closely match the requirements of the ITRS [3] for high-performance devices in the 25, 20 and 14 nm technology generation, which correspond to 10, 7.5 and 5 nm channel length devices, respectively.

We have shown that next generation UTB-SOI MOSFETs are affected by different sources of intrinsic parameter fluctuations, which can become a major factor in limiting further scaling and integration. As expected, the combined sources of IPF cause the worst fluctuations, compared with each individual source of IPF. Random discrete dopants in the source–drain region of UTB-SOI MOSFETs are the dominant source of intrinsic parameter fluctuations. However for the line edge roughness and body thickness variations, the geometry and scale of the devices will dictate which of these two sources of fluctuations dominates and it is therefore important to investigate each source individually, and in combination with others to obtain the full picture. Even ignoring the clear fabrication challenges and transport limitations which may effect nanoscale UTB-SOI MOSFETs, from the perspective of intrinsic parameter fluctuations, scaling to channel lengths of 10 nm and below will be extremely difficult. With random dopants in the source–drain regions acting as a major source of IPF, a transition to Schottky source–drain devices may be a necessary viable alternative.