بررسی اکتشاف باکتری توسط سیستم های چند مرحله ای با قابلیت اطمینان بر اساس تقارن قدرت در سنتز سطح بالا

Technology evolution and energy of particle impact both plays a major role in inducing multi-cycle transient fault (longer duration transient) in a device. However, designing an optimized multi-cycle fault tolerant system is non-trivial. This paper presents a novel design space exploration (DSE) approach for multi-cycle transient fault tolerant datapath based on user power-delay constraints during high level synthesis (HLS). To the best of the authors’ belief, this is the first work to solve this problem in the literature so far. More specifically, the current work in the literature so far utilizes ‘triple modular redundancy (TMR)’ to design a fault tolerant datapath, however, this paper proposes a ‘dual modular redundancy (DMR) design with equivalent circuit’ scheme to achieve the same. The novel equivalent circuit that works with DMR systems performs the function of extracting the correct output from the DMR design. Further, the proposed work is the first work in the literature that handles multi-cycle transient faults during design space exploration of fault tolerant datapath. Therefore, key contributions of this paper are as follows: (a) novel multi-cycle transient fault tolerant algorithm that has capability to isolate original and duplicate units in a DMR with respect to the transient fault; (b) novel DSE approach that combines our fault tolerant algorithm along with user specified conflicting power-performance constraint that guides this intractable search problem to reach an high quality fault tolerant solution without violating the power budget and delay requirement; (c) integrates a heuristic based on bacterial foraging optimization algorithm (BFOA) that performs adaptive searching. Finally, results indicated an average improvement in Quality of Results (QoR) of >24% and reduction in hardware usage of >57% of the final solution compared to similar approach.