روش مدل سازی بازده ساده شده برای طراحی قانون تجارت کردن در لایه های اتصال

In this paper, we present a pre-layout yield estimation approach to assess the impact of changing design rules to overall substrate cost. Introducing a density factor for interconnect substrates together with a simplified yield model, thus accelerating the “short failure” critical area estimation, a preliminary design rule trade-off is feasible. In order to assess a possible cost impact when changing the design rules, we used a nine-chip Pentium multi-chip module as a case study, where we re-calculated substrate sizes and first pass yields using our model. The results showed that there is only a narrow window of opportunity to profit economically from altering the rules.

High-density substrates are not only required for multi-chip modules (MCMs), present in some of today’s leading edge telecommunication and communication products, but also for chip size/scale packages using interposers. The cost for this type of substrates is high, mainly due to the small production panel size operating on outdated 4-in. or 5-in. wafer diameter semi-conductor equipment. In order to improve the cost effectiveness, the European Union Esprit project LAP (Low cost large area panel processing of MCM-D substrates and packages) consortium had the target to setup a large-panel production ranging from 12×12 in.2 to View the MathML source and to bring down the cost using both production scaling and new materials [1]. While today’s View the MathML source thin-film processes are mature and operate under tight control, the new LAP processes are more sensitive to dust particles and other spot defects, exhibiting higher defect density. The reason is that larger clean-room environments are required to process large panels and that the thin-film processes themselves are more difficult to control. Examples for “short/open” defects found on LAP test vehicles so far are shown in Fig. 1(a)–(c). As customers now face lower yield and thus higher cost, the question arises if the use of “relaxed” design rules that are less sensitive to defects can compensate this lower yield.Given a defect size distribution s(x), the widening of the signal line width and the line–line spacing (“increasing the design rules”), increases the minimum size x0 of a defect causing a failure. Consequently, the total number of defects that can cause a functional error decreases. An example is depicted in Fig. 2(adopted from Ref. [2]), where due to expanded line width the fatal defect size x0,A becomes x0,B.On the other hand, the error-susceptible area (the area where the center of a circular-shaped defect the size x has to lie on, commonly referred to as “critical area” CA) grows because there is more interconnection area. Moreover, relaxing the design rules might enlarge the substrate size and therefore its cost. Thus, when relaxing the design rules to be beneficial, the gains due to higher yield have to surpass possible substrate cost increases. Existing work [3] has been confined on the development of local design rules to reduce local fault clusters. But currently, no methodology is available to find the optimum global design rules. With our work we close this gap allowing for a yield-cost trade-off for high-density interconnect (HDI) substrates. The paper is organized as follows: first, we briefly review the history and aspects of yield modeling and critical area extraction, then we detail our underlying assumptions and develop the yield vs. line width model. With a case study of a Pentium MCM [4], we quantify the impact on final substrate costs. The results are then discussed, conclusions are drawn, and a brief outlook is given.

In this paper we adopted a simple Poisson yield model that can quantify the impact of various defect densities and design rules to overall substrate yield for “open/short” defects. Due to the limitation of applications to interconnect substrates only “line open” and “line–line short” defect types are present. The critical area for “line-open” defects has been approximated using the total interconnect length, the “line–line short” defect type by estimating the percentage of lines running parallel, expressed by a density factor. The proposed density factor is a simple and efficient means to estimate the contribution of the “line–line short” failure without requiring extensive critical area extraction using geometrical or even Monte Carlo methods. A weak point is that currently the density factor can be estimated only roughly. Future work will focus on a density factor estimation based on a library of designs. Analyzing the result figures of our Pentium MCM case study, we can say that using yield improvement by increasing design rules can lead to a more cost effective substrate, although the window of opportunity is small. Prerequisite is that the increase of the substrate design rules has minimal impact to the overall substrate area. As the overall wiring length has more influence on the yield curve than the density factor, this calculation could be refined using the global routing approach proposed by Hirt and implemented in JavaCAD [17]. Once stable defect density data of the LAP project will be available, we will be able to tell whether increased design rules can decrease overall cost. Additionally, switching to the negative binomial yield model could improve the prediction quality.