صورت خطی متغیر با سطح کاشت n-لایه مورد استفاده برای بهبود تجارت کردن بین ولتاژ شکست و روی مقاومت ترانزیستور RESURF LDMOS

A new RESURF LDMOS transistor using a linearly varying surface-implanted doped (LVD) n− layer is reported. Detailed numerical simulations demonstrate the characteristics of this device incorporating an LVD n− layer and indicate an enhancement on the performance in comparison to an optimal conventional structure with an uniform epi-layer concentration.

In recent years, a called reduce surface field (RESURF) lateral device technology for power IC incorporating an uniform n− epi-layer of the drift region on the substrate silicon wafer has been presented for enabling the lateral breakdown voltage to be increased [1]. This has lead to the rapid development of a low cost high voltage IC process technology. In early bulk silicon technology, a lateral non-uniform doping profile has been presented to avoid low breakdown voltage caused by the radius of curvature of the metallurgical junction [2]. Continuous graded junction terminations [3] and [4] are also used for the same purpose. Extending the RESURF principle to SOI technology, Merchant et al. developed a theoretical model for optimizing the breakdown voltage of thin film SOI RESURF LDMOS transistor [5], which predict that the linear lateral doping profile in the drift region on SOI can attain maximum breakdown voltage for SOI RESURF LDMOS [6] and [7]. A computer program was developed for realization of the linear lateral doping profile and the experimental verifications were also performed [8] and [9]. However, these results were only available for the thin film SOI RESURF LDMOS devices. As it is well known, the advantages and applications of thin film SOI technology using the RESURF principle are countered somewhat by high cost of the SOI substrate materials and self-heating of the high-voltage power devices. In this letter, the role of a similar linearly varying surface-implanted doped (LVD) n− layer implemented at the n− epi-layer surface of an RESURF LDMOS is investigated using a 2-D device simulation program, medici[10]. The characteristics of this device have been demonstrated compared to an optimal conventional RESURF device and an improvement on the trade-off between the breakdown voltage and on-resistance has been reported.

The results presented in this letter clearly indicate that the performance of an RESURF LDMOS can be significantly improved with use of a linearly varying surface-implanted n− layer in lieu of a uniformly doped n− layer. The significant characteristics of this device have been well demonstrated by the numerical simulations. This technology is also well suited for a fully implanted process technology.