The reliability of analog integrated circuits becomes a major concern for the semiconductor industry as technology continuously scales. Among the many contributing factors, manufacturing process induced parameter variations and lifetime operational-condition-dependent transistor aging are two major hurdles limiting the reliability of analog circuits. Process variations mainly influence the parametric yield value of the fresh circuits, while transistor aging due to physical effects, such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI), will cause another yield loss during circuit lifetime. In the past decades, the two issues were mainly studied separately by various communities, but analog designers nowadays need an accurate yet efficient method to analyze and optimize their circuits during the design phase, to ensure a more robust design tolerant of such joint effects.
This paper proposes an efficient method for sizing of analog circuits for reliability. It is based on the analysis and optimization of the fresh worst-case distance value for each circuit performance, which can be used to characterize the robustness of circuits considering process variations and aging effects in terms of x-sigma. The fresh and aged sizing rules as well as the maximum area constraints are checked during the optimization. The trade-off between the circuit lifetime and the price we pay in terms of layout area is studied in detail. According to the result of this trade-off analysis, a longer circuit lifetime requires more total area to be spent in layout, and designers can ensure the circuit robustness with certain layout area consumption.
The continuous scaling of semiconductor technology into nanometer scale contributes to higher chip densities, improved circuit performances, lower cost per transistor, as well as several challenges and side effects, which will limit the product yield value after manufacturing and in circuit lifetime. Among those hazards, influential problems arise from manufacturing process variations and transistor degradation-related lifetime circuit reliability. These have been the major concern for both circuit design and chip manufacturing communities for decades, since these will result in parametric yield loss, early wear-out, and extra redesign costs [1].
Most of the past works quantify the influences of process variations and lifetime degradations separately. The analysis and optimization of analog circuits considering process variations alone have been in research for decades, and certain design centering algorithms and commercial software are available to achieve a design for yield (more specifically, fresh yield) [2] and [3]. On the other hand, the modeling of device parameter degradations such as NBTI and HCI has been so far focusing mainly on the nominal values without considering the underlying variations during manufacture process [4] and [5]. Solutions towards transistor aging effects alone include initial over-design of gate size [6], adding additional monitor circuitry [7], adaptive body biasing scheme [8], etc.
The reliability problem gets even worse if the joint effects of both process variations and transistor aging are considered, since they co-exist in reality both spatially across wafers and temporally over operational time. An example is illustrated in Fig. 1, where 300 Monte-Carlo simulations are run on a fresh and 5-year-old Miller amplifier with a current industrial technology. Values of Gain-Bandwidth Product (GBW) and DC Gain are shown, both moving towards negative directions. Such shifts of performance distribution result from drifts of transistor parameters, such as vth, due to NBTI and HCI. Certain samples of the circuits fall out of the possible performance specifications during operational time, resulting in an early wear-out, or in other words, a shorter lifetime than expected.It is only since recent years that the joint effects of process variations and parameter aging are considered. Authors in [9] propose an aging-aware statistical timing analysis framework for digital circuits and perform a gate sizing algorithm based on the criticality of the gate during aging. The influence of variations of NBTI itself is further studied in [10]. For analog circuits, authors in [11] present a simulation framework considering the joint effects based on a response surface model of the circuit behavior. While the framework can identify those critical parameters on the circuit reliability, a quantified solution is not available which is needed for analog circuit sizing. Authors in [12] propose a two-step optimization flow to analyze and optimize the aged yield value of the analog circuits. While the idea of [12] is simple, it is very time-consuming since another step of aged yield optimization is needed on top of the traditional fresh yield optimization process.
This paper proposes an efficient method for sizing of analog circuits for reliability. It is based on the analysis and optimization of the fresh worst-case distance value for each circuit performance, which can be used to characterize the robustness of circuits considering process variations and aging effects in terms of x-sigma. The trade-off between the circuit lifetime and the price we pay in terms of layout area is studied in detail. According to the result of this trade-off analysis, a longer circuit lifetime requires more total area to be spent in layout, and designers can ensure the circuit robustness with certain layout area consumption.
Process variations and parameter lifetime degradations are becoming more serious as technology continuously scales, which makes design-for-reliability a more difficult task. This paper proposes a method for analog circuit optimization considering such joint effects based on worst-case distances with consideration of maximum area constraints and fresh and aged sizing rules. The trade-off between design robustness and area overhead is analyzed in detail, and is available for designers to choose from. A more reliable design requires more layout area.
