تأثیر اندازه لاتین بر عملکرد تولید در تولید ویفر بر اساس شبیه سازی

Semiconductor manufacturing has been a significant change over the past decades. Nevertheless, from production efficiency point of view, it should be argued with validity whether 25-wafer is an adaptive lot size in the future to fulfill the manufacturing processes. In this work, a simulation model to study the relationship between lot size and the performances of wafer fabrication is proposed. Three production performance indices are taken into account in this model including cycle time of products, total throughput and the waiting time of WIP by workstation. Based on the simulation result, it reveals that the cycle time of products is synchronously decreased when the lot size is shrunk. However, the waiting time of WIP is not coincident with lot downsizing. From these results, the model of this study can provide a trend to establish the best lot size to fulfill the current and future wafer fabrication.