Modern flip chip technologies for imaging applications have achieved a very high integration level together with the possibility of large area assemblies. These developments have resulted in an enormous increase in the total number of bump bonds per assembly. Consequently, yield tests become difficult, and an accurate measurement of it is often discarded. This problem is aggravated in medical applications, where the critical information can be limited to a few pixels, and therefore, yield should be very close to 100%. In these cases, a variation of a small percentage in bump bond yield can make the difference between an usable and a non-usable assembly. Therefore, quantitative and precise measurement of bump bond yield is needed to characterize the quality of any high density flip chip technology for these applications. In this paper, we present a newly developed test structure for electrical measurement of the bump bond yield of high density flip chip technologies, allowing both optimization and statistical control of the process. This test structure facilitates the identification of possible process deviations with precise quantitative yield measurements. It also allows to pin point any localized systematic failure in the bump bonding process. The test structure has been used to evaluate the yield of different flip chip technologies and has contributed to their fine optimization where necessary.
Modern detector applications, for X-ray and gamma ray imaging, make use of high density pixel arrays that should be connected with their corresponding readout electronics by means of bump bonding or flip chip technologies. The technology developments achieved lately have increased the density of the pixel arrays by drastically reducing the bump size and the separation between bond pads (pad-pitch). Moreover, the assembly size has increased considerably following a general trend in silicon technologies. These developments have resulted in an enormous increase in the total number of bump bonds per assembly reaching numbers as high as 1 million bump bonds per assembly [1]. As this number increases, quality and yield evaluation of the flip chip technologies becomes difficult, and therefore, an accurate control of the bump bond yield is often discarded to work merely with general estimations of its value.
Test structures and full test chips have been used so far, but only for bond quality tests or for partial yield estimations [2] and [3]. X-ray, infrared or scanning acoustic microscopy (CSAM) are imaging methods that are also applied for yield estimation [4], but they can overpass some electrical problems and they are impractical for quantitative measurements in large assemblies.
The problem is aggravated in applications involving medical imaging, since the critical information can be limited to a few pixels, and therefore, yields should be very close to the 100%. In these cases, a variation of a small percentage in bump bond yield can make the difference between a usable and a non-usable assembly. Moreover, the recent introduction of new techniques and materials in the bump bonding processes [5] makes previous yield figures in the hands of the manufacturers not valid anymore for these new technologies and emphasize the need of properly updated yield measurements.
For these reasons, precise and quantitative measurements of bump bond yield are needed to characterize the quality of modern flip chip technologies, but, at the moment, there is not a valid tool in the hands of the manufacturers to obtain accurate yield figures of their flip chip technologies. In the same way, there is not a valid method for the end users, like image application developers, to compare among different manufacturers in terms of yield figures. The only possibility is to directly use their “precious” real detectors and chips in test prototypes and estimate the bump bond yield with the resulting images from those prototypes. This has the inconvenient that there is no way to know whether a bad image pixel comes from bump bonding problems or problems in the original detector or chip, or even in the readout system.
In this paper, we present a newly developed test structure that allows quantitative electrical characterization of the bump bond yield of a technology, allowing statistical control of the process. The test structure consists of a full assembly with a practical number of long bump bond daisy chains evenly distributed across the whole assembly. By measuring the conductivity of these chains through the whole assembly, the bump bond yield can be obtained with a statistical calculation. The number of bump bonds per chain can be tuned in order to adjust the test to the yield ranges of interest for the particular application. This test structure has been used on different flip chip technologies in order to measure their yield and perform quantitative comparisons.
A new test structure has been designed and fabricated to accurately measure the bump bond yield in high density flip chip technologies. This structure has been validated using it for bump bond yield evaluation of assemblies from two different manufacturers. The test structure provides a precise quantitative evaluation of bump bond yield, which can be used for comparison among different flip chip technologies and manufacturers. Also, manufacturers can use this test structure to characterize and optimize their processes. The structure is, in addition, a valid tool for quality control of the flip chip process and for production control, as it allows manufacturers to identify deviations of the process characteristics before they lead to drastic reductions of the bump bond yield.
Although this structure does not cover the effects of the bump bonding process on the performance of detectors, it is a very useful tool to identify and separate assembly problems related directly to the bump bonding process itself. By the precise information on bump bond yield that it provides, manufacturers and end users can have a better insight on the performance and limits of their final imaging system.
