منابع حافظه زمانیکه سیاست برنامه ریزی خودکار برای سیستم های چند هسته ای اجرا می شود

Traditionally, the computer architect improves the system performance by integrating multiple types of processing cores and memory systems. However, there is relatively limited work done on investigating data transfers on the memory systems and scheduling the memory data transfers at the hardware level. Furthermore, the variable and unpredictable nature of the applications data transfers create unfair memory resource utilization that reduce the overall performance of a system. In this paper, a Memory Resource Aware Pattern-based Controller (MRAPC) is proposed and designed. MRAPC organizes the data transfers in pattern descriptors, prioritizes them with respect to the number and size of the transfer requests and manages the local and main memories. In order to measures the performance and effectiveness, the MRAPC is integrated into high performance ARM processing, FPGA based prototyping and Tasksim based Simulation enrichments. When compared to the baseline ARM and FPGA based multi-core systems, the FPGA and ARM based MRAPC systems achieve up to 2.15× and 1.91× performance respectively. While comparing the results of simulator environment, the MRAPC transfers data-structures up to 5.09× faster.